公开(公告)号：US20130126215A1

公开(公告)日：2013-05-23

申请号：US13489045

申请日：2012-06-05

Applicant: Suk Hyeon Cho ,  Francis Sohn

Inventor： Suk Hyeon Cho ,  Francis Sohn

IPC: H05K7/20 ,  H05K3/42

CPC classification number: H05K1/0206 ,  H05K1/0209 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09781 ,  H05K2203/0338 ,  Y10T29/49165

Abstract: The present invention relates to a printed circuit board including: a substrate; a circuit pattern formed on a surface of the substrate; a dummy pattern formed on the surface of the substrate, where the circuit pattern is not formed, to be spaced apart from the circuit pattern by a predetermined interval; and a plurality of heat radiating vias formed along an outer edge of the substrate to electrically connect the dummy patterns through the substrate, and it is possible to suppress generation of electromagnetic waves or shield the electromagnetic waves and improve heat radiating characteristics at the same time.

Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，包括：基板; 形成在所述基板的表面上的电路图案; 形成在基板表面上的虚设图案，其中未形成电路图案，以与电路图案间隔预定间隔; 以及沿着基板的外缘形成的多个散热通孔，以通过基板电连接虚拟图案，并且可以同时抑制电磁波的产生或屏蔽电磁波并提高散热特性。

公开(公告)号：US20130112463A1

公开(公告)日：2013-05-09

申请号：US13512271

申请日：2010-11-25

Applicant: Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

Inventor： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

IPC: H05K3/10 ,  H05K1/09 ,  H05K1/03 ,  H05K1/02

CPC classification number: H05K3/101 ,  H05K1/02 ,  H05K1/0353 ,  H05K1/092 ,  H05K3/02 ,  H05K3/108 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2203/0278

Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.

Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。

公开(公告)号：US08362366B2

公开(公告)日：2013-01-29

申请号：US13006222

申请日：2011-01-13

Applicant: Tsugio Ambo ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

Inventor： Tsugio Ambo ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

IPC: H05K1/11

CPC classification number: H05K3/202 ,  H01R9/2466 ,  H01R12/523 ,  H05K3/041 ,  H05K3/222 ,  H05K3/308 ,  H05K3/326 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/4611 ,  H05K13/0061 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10401 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2203/081 ,  H05K2203/082 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board includes a foil circuit provided on a synthetic resin plate formed by injection molding, made of a copper foil, and having a pattern different for the circuit board. Anchor pins projecting upward are provided on the resin plate and passed through pinholes made in the foil circuit. The foil circuit is positioned and secured to the resin plate. In a required portion of the resin plate, a terminal insertion hole is provided, and a receiving terminal is secured to the required portion of the terminal insertion hole and connected to the foil circuit.

Abstract translation: 电路板包括设置在通过注射成型形成的合成树脂板上的箔电路，由铜箔制成并且具有不同于电路板的图案。 在树脂板上设置向上突出的定位销，并穿过箔片电路中制成的针孔。 箔片电路定位并固定到树脂板上。 在树脂板的所需部分中，设置有端子插入孔，并且接收端子固定到端子插入孔的所需部分并连接到箔片电路。

公开(公告)号：US20130008025A1

公开(公告)日：2013-01-10

申请号：US13621122

申请日：2012-09-15

Applicant: Heung-Kyu KIM

Inventor： Heung-Kyu KIM

IPC: H05K3/10

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0221 ,  H05K3/205 ,  H05K2201/0376 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.

公开(公告)号：US08261436B2

公开(公告)日：2012-09-11

申请号：US12646384

申请日：2009-12-23

Applicant: Chen-Yueh Kung

Inventor： Chen-Yueh Kung

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit substrate fabricating process includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. In addition, a fabricating process for the circuit substrate is also provided.

Abstract translation: 电路基板制造工艺包括基底层，图案化导电层，电介质层，外垫和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。 此外，还提供了用于电路基板的制造工艺。

公开(公告)号：US08222532B2

公开(公告)日：2012-07-17

申请号：US13150691

申请日：2011-06-01

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K1/03 ,  H01K3/10

CPC classification number: H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

Abstract translation: 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US20120175162A1

公开(公告)日：2012-07-12

申请号：US13428523

申请日：2012-03-23

Applicant: Jee Soo MOK ,  Jun Heyoung PARK

Inventor： Jee Soo MOK ,  Jun Heyoung PARK

IPC: H05K1/11

CPC classification number: H05K3/4069 ,  H05K3/107 ,  H05K3/386 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2203/0278 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T156/109

Abstract: A printed circuit board having an insulating layer; circuit patterns formed on both surfaces of the insulating layer in order to be embedded in the insulating layer; and a bump formed to pass through the insulating layer in order to electrically connect the circuit patterns formed on both surfaces of the insulating layer.

Abstract translation: 一种具有绝缘层的印刷电路板; 形成在绝缘层的两个表面上的电路图案，以便嵌入绝缘层中; 以及形成为穿过绝缘层的凸块，以便电连接形成在绝缘层的两个表面上的电路图案。

公开(公告)号：US08215011B2

公开(公告)日：2012-07-10

申请号：US12379307

申请日：2009-02-18

Applicant: Seok Hwan Ahn ,  Young Gwan Ko

Inventor： Seok Hwan Ahn ,  Young Gwan Ko

IPC: H01J3/10

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1461

Abstract: Disclosed is a printed circuit board having a plating pattern buried in a via and a method of manufacturing the same. The method of manufacturing the printed circuit board includes forming a negative pattern for forming a plating pattern, thus remarkably reducing the generation of plating thickness deviation in a plating process for forming a circuit pattern, and the printed circuit board has improved electrical signal transmission properties.

Abstract translation: 公开了一种印刷电路板及其制造方法。 制造印刷电路板的方法包括形成用于形成电镀图案的负图案，从而显着减少了用于形成电路图案的电镀工艺中电镀厚度偏差的产生，并且印刷电路板具有改善的电信号传输性能。

公开(公告)号：US20120152601A1

公开(公告)日：2012-06-21

申请号：US13374858

申请日：2012-01-19

Applicant: Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05K1/03 ,  B23K1/20 ,  B23K31/02 ,  B05D5/12 ,  B05D3/00

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Abstract translation: 描述了用于封装衬底和管芯间隔件的层或层。 层或层包括位于平面内并由金属通孔分开的多个陶瓷阱。 陶瓷井内的凹陷由介电填料材料占据。

公开(公告)号：US08169071B2

公开(公告)日：2012-05-01

申请号：US13019562

申请日：2011-02-02

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/04

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。