公开(公告)号：US20090288874A1

公开(公告)日：2009-11-26

申请号：US12483223

申请日：2009-06-11

Applicant: George Dudnikov, JR. ,  Franz Gisin

Inventor： George Dudnikov, JR. ,  Franz Gisin

IPC: H05K1/00

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过导电层，电介质层和电镀抗蚀剂在PCB堆叠中钻出通孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。

公开(公告)号：US07615709B2

公开(公告)日：2009-11-10

申请号：US11978810

申请日：2007-10-30

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。

公开(公告)号：US20090268419A1

公开(公告)日：2009-10-29

申请号：US12436996

申请日：2009-05-07

Applicant: Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

Inventor： Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

IPC: H05K7/12

CPC classification number: H05K1/023 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0233 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

公开(公告)号：US20090268418A1

公开(公告)日：2009-10-29

申请号：US12437042

申请日：2009-05-07

Applicant: Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

Inventor： Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

IPC: H05K1/18

CPC classification number: H05K1/023 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0233 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

Abstract translation: 这里公开了具有嵌入其中的RF模块功率级电路的印刷电路板。 具体地说，本发明涉及一种具有嵌入其中的RF模块功率级电路的印刷电路板，其中在多层有线电路板的电源平面上限定或形成用于电阻器，焊道或电感器的端子焊盘， 将电阻器，焊道或电感器连接到电源平面，并且电阻器，焊道或电感器通过使用通孔或通过嵌入电阻器，焊道或电感器而与去耦电容器并联连接 垂直于电源平面，从而减小RF模块的尺寸并提高其性能。

公开(公告)号：US07594105B2

公开(公告)日：2009-09-22

申请号：US11566942

申请日：2006-12-05

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K7/08 ,  H01P5/02

CPC classification number: G06F1/189 ,  G06F1/188 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.

Abstract translation: 本发明有效地防止半导体装置的电源端子的电位波动，即噪声流出到主电源配线。 多层印刷电路板包括第一电源通孔，其连接到第一表面层上的半导体集成电路的电源端并从第一表面层延伸到第二表面层;接地通孔，其连接到 接地导电层从接地导电层延伸到第二表面层，并且通过旁路电容器连接到第二表面层上的第一电源通孔，形成在电源导电层中的第一间隙孔，以及 形成在接地导电层中的第二间隙孔。 第一间隙孔大于第二间隙孔。

公开(公告)号：US20090175011A1

公开(公告)日：2009-07-09

申请号：US12401127

申请日：2009-03-10

Applicant: Takashi KARIYA

Inventor： Takashi KARIYA

IPC: H05K1/18 ,  H05K7/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract translation: 当具有内置电容器的封装衬底包括通过高电介质层43中的针孔P彼此电短路的第一薄膜小电极41aa和第二薄膜小电极42aa时， 在第一薄膜小电极41aa中没有形成供电支柱61a和通孔61b，也不在第二薄膜小电极42aa中形成接地柱62a和通孔62b。 结果，短路的小电极41aa和42aa既不与电源线也不与接地线电连接，并且成为独立于电源电位和接地电位的电位。 因此，在薄膜电容器40中，只有短路的小电极41aa和42aa夹着高电介质层43的部分失去电容器功能，其他薄膜小电极41a和42a夹住高电介质的部分 层43保持电容器的功能。

公开(公告)号：US07525175B2

公开(公告)日：2009-04-28

申请号：US11341485

申请日：2006-01-30

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H01G2/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract translation: 当具有内置电容器的封装衬底包括通过高电介质层43中的针孔P彼此电短路的第一薄膜小电极41aa和第二薄膜小电极42aa时， 在第一薄膜小电极41aa中没有形成供电支柱61a和通孔61b，也不在第二薄膜小电极42aa中形成接地柱62a和通孔62b。 结果，短路的小电极41aa和42aa既不与电源线也不与接地线电连接，并且成为独立于电源电位和接地电位的电位。 因此，在薄膜电容器40中，只有短路的小电极41aa和42aa夹着高电介质层43的部分失去电容器功能，其他薄膜小电极41a和42a夹住高电介质的部分 层43保持电容器的功能。

公开(公告)号：US20090091406A1

公开(公告)日：2009-04-09

申请号：US12249273

申请日：2008-10-10

Applicant: Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

Inventor： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC: H01P1/00

CPC classification number: H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

Abstract translation: 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US07514789B1

公开(公告)日：2009-04-07

申请号：US12147411

申请日：2008-06-26

Applicant: Yuming Tao ,  Jon M. Long ,  Anilkumar Raman Pannikkat

Inventor： Yuming Tao ,  Jon M. Long ,  Anilkumar Raman Pannikkat

IPC: H01L23/48

CPC classification number: H05K1/0243 ,  H01L23/49838 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09718 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Abstract translation: 封装板协同设计方法保留了从半导体封装到应用PCB的高速信号的信号完整性。 封装和PCB之间互连的最佳架构增强了信号传播，使寄生电平最小化，并降低了来自相邻高频信号的电磁干扰。 本发明导致具有优异信号质量和EMI屏蔽性能的装置，具有增强的以千兆比特每秒比特率传送数据流的能力。

公开(公告)号：US20090061684A1

公开(公告)日：2009-03-05

申请号：US12203270

申请日：2008-09-03

Applicant: Thomas S. Cohen ,  Marc B. Cartier, JR. ,  Mark W. Gailus

Inventor： Thomas S. Cohen ,  Marc B. Cartier, JR. ,  Mark W. Gailus

IPC: H01R24/00 ,  H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。