公开(公告)号：US5661087A

公开(公告)日：1997-08-26

申请号：US476623

申请日：1995-06-07

Applicant: David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

Inventor： David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

IPC: H01L25/00 ,  H01L21/60 ,  H01L21/98 ,  H01L23/373 ,  H01L23/482 ,  H01L23/485 ,  H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06 ,  H01R4/04 ,  H01R29/00 ,  H05K3/30 ,  H05K3/32 ,  H05K7/02

CPC classification number: H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01R29/00 ,  H01R4/04 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L29/0657 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.

Abstract translation: 一种用于垂直互连硅片段叠层的方法和装置。 每个段在半导体晶片上包括多个相邻的管芯。 使用一个或多个金属互连层在片段上互连多个管芯，该金属互连件延伸到段的全部四个侧面，以提供用于外部电连接点的边缘焊盘。 在芯片互连后，使用斜切切割从晶片的背面切割每个片段，以在每个片段上提供四个向内倾斜的边缘壁。 在从晶片切割片段之后，将片段放置在彼此的顶部以形成叠片。 堆叠中的垂直相邻段通过将导电环氧树脂施加到堆叠的所有四个侧面而电互连。 堆叠中的每个段的向内倾斜的边缘壁提供凹部，其允许导电环氧树脂在片段堆叠之后接近每个片段上的边缘接合焊盘和侧向电路。 然后将电互连段的堆叠安装在电路板的表面下方，并通过在堆叠顶部的接合焊盘和电路板之间施加迹线的导电环氧树脂电连接到电路板上的电路。

公开(公告)号：US5545466A

公开(公告)日：1996-08-13

申请号：US500540

申请日：1995-07-11

Applicant: Muneo Saida ,  Yutaka Hirasawa ,  Katsuhiro Yoshimura

Inventor： Muneo Saida ,  Yutaka Hirasawa ,  Katsuhiro Yoshimura

IPC: H05K3/38 ,  B32B9/00

CPC classification number: H05K3/384 ,  H01L2924/0002 ,  H05K2201/0355 ,  H05K2201/10477 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0392 ,  H05K2203/0723 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804

Abstract: The present invention provides a copper-clad laminate characterized in that an electrolytic copper foil on the glossy (shiny) surface side of which a copper electrodeposit is formed, is bonded at its glossy surface side to one side or each of both sides of a substrate, which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. The present invention further provides a copper-clad laminate which can be suitably employed in the production of such a printed wiring board.

Abstract translation: 本发明提供一种覆铜层压板，其特征在于，在形成有铜电沉积物的光泽（光泽）表面侧上的电解铜箔在其光泽表面侧与衬底的两侧或每一侧接合 ，其具有细间距布线（电路）图案并且具有高蚀刻因子。 本发明还提供一种覆铜层压板，其可以适用于制造这种印刷线路板。

公开(公告)号：US5495223A

公开(公告)日：1996-02-27

申请号：US168184

申请日：1993-12-17

Applicant: Ziro Honda ,  Takashi Takahashi

Inventor： Ziro Honda ,  Takashi Takahashi

IPC: H05K1/18 ,  H01C1/144 ,  H05K3/34

CPC classification number: H05K3/3426 ,  H01C1/144 ,  H05K3/3442 ,  H05K2201/10477 ,  H05K2201/10636 ,  H05K2201/10916 ,  Y02P70/611 ,  Y02P70/613

Abstract: A hybrid integrated circuit device includes a circuit board having at least two electrical conductors; a chip resistor bridgingly disposed across two of the electrical conductors of the circuit board; and solder electrically connecting the chip resistor to the two electrical conductors. The chip resistor has an electrically insulating substrate, two electrodes disposed on the electrically insulating substrate, separated from each other, and each electrode has a contact end electrically contacting the electrical conductors of the circuit board and a resistor element disposed on the electrically insulating substrate and electrically connected to the contact ends of the electrodes. The solder electrically connects the electrodes of the chip resistor to the electrical conductors of the circuit board.

Abstract translation: 混合集成电路装置包括具有至少两个电导体的电路板; 桥接电路，跨过电路板的两个电导体; 以及将芯片电阻器与两个电导体电连接的焊料。 芯片电阻器具有电绝缘基板，设置在电绝缘基板上的两个电极彼此分离，并且每个电极具有与电路板的电导体和设置在电绝缘基板上的电阻元件电接触的接触端， 电连接到电极的接触端。 焊料将芯片电阻器的电极与电路板的电导体电连接。

公开(公告)号：US5437914A

公开(公告)日：1995-08-01

申请号：US143849

申请日：1993-10-26

Applicant: Muneo Saida ,  Yutaka Hirasawa ,  Katsuhiro Yoshimura

Inventor： Muneo Saida ,  Yutaka Hirasawa ,  Katsuhiro Yoshimura

IPC: B32B15/08 ,  C25D1/04 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38 ,  B32B9/00

CPC classification number: H05K3/384 ,  H01L2924/0002 ,  H05K2201/0355 ,  H05K2201/10477 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0392 ,  H05K2203/0723 ,  Y10S428/901 ,  Y10S428/935 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804

Abstract: The present invention provides a copper-clad laminate characterized in that an electrolytic copper foil on the glossy surface side of which a copper electrodeposit is formed, is bonded at its glossy surface side to one side or each of both sides of a substrate, which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. The present invention further provides a copper-clad laminate which can be suitably employed in the production of such a printed wiring board.

Abstract translation: 本发明提供一种覆铜层压板，其特征在于，在其光刻面侧形成有铜电沉积物的电解铜箔在其光泽面侧与基板的两面的一面或每一面接合， 细间距布线（电路）图案并且具有高蚀刻因子。 本发明还提供一种覆铜层压板，其可以适用于制造这种印刷线路板。

公开(公告)号：US5426405A

公开(公告)日：1995-06-20

申请号：US366000

申请日：1994-12-29

Applicant: Daniel J. Miller ,  Kim H. Chen ,  Lewis R. Dove ,  Vaddoarahalli K. Nagesh

Inventor： Daniel J. Miller ,  Kim H. Chen ,  Lewis R. Dove ,  Vaddoarahalli K. Nagesh

IPC: H01L23/50 ,  H01L23/40 ,  H01P1/02 ,  H01P3/08 ,  H01P5/08 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01L23/32

CPC classification number: H01L23/66 ,  H01L23/4006 ,  H05K1/141 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4087 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0286 ,  H05K2201/10393 ,  H05K2201/10477 ,  H05K2201/10946 ,  H05K3/325 ,  H05K3/3421 ,  H05K3/368

Abstract: A family of modular hybrid assemblies with high frequency interconnections is effected by a high frequency circuit assembly attached to a motherboard. Each assembly comprises standardized conducting elements and customizable transitions and circuit regions. The customizable transitions can be placed anywhere along the conducting element and are capable of low and high frequency performance. Attachment of the assembly can be effected via a standardized clamping structure which compresses an elastomeric member upon the conducting elements or by bending the conducting elements and soldering on end to attachment sites on the motherboard. Each member of the family of modular hybrid assemblies provides a controlled impedance transition from a transmission line on the circuit assembly to a transmission line on the motherboard.

Abstract translation: 具有高频互连的一系列模块化混合组件由附接到母板的高频电路组件实现。 每个组件包括标准化的导电元件和可定制的转变和电路区域。 可定制的转换可以放置在导电元件的任何地方，并且能够实现低频和高频性能。 组件的附接可以通过标准化的夹紧结构实现，该结构将弹性构件压缩在导电元件上，或通过弯曲导电元件并在端部焊接到主板上的附接位置。 模块化混合组件系列的每个成员提供从电路组件上的传输线到主板上的传输线的受控阻抗转变。

公开(公告)号：US5261155A

公开(公告)日：1993-11-16

申请号：US14291

申请日：1993-02-05

Applicant: Christopher G. Angulas ,  Patrick T. Flynn ,  Joseph Funari ,  Thomas E. Kindl ,  Randy L. Orr

Inventor： Christopher G. Angulas ,  Patrick T. Flynn ,  Joseph Funari ,  Thomas E. Kindl ,  Randy L. Orr

IPC: H01L23/498 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L23/49816 ,  H01L23/4985 ,  H01R12/52 ,  H05K3/363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/141 ,  H05K2201/0394 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K3/3452 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144

Abstract: A method of bonding a flexible circuitized substrate to a circuitized substrate (e.g., printed circuit board) to interconnect selected circuitry of both substrates using solder. Solder paste is applied over conductive pads on the circuitized substrate and organic dewetting material (e.g., epoxy coating) adjacent thereto. The flexible substrate, having conductors located within and/or traversing an aperture in the flexible substrate's dielectric, is positioned above the solder paste and heat is applied (e.g., in an oven). The paste, dewetting from the organic material, "balls up" and substantially surrounds a solder member (ball) attached to a bridging portion of the flexible substrate's conductor, thereby connecting both substrates. A frame member may be used to align the flexible substrate, both during solder member attachment thereto, as well as for aligning the flexible substrate having solder members attached, to the respective solder paste locations on the lower substrate.

Abstract translation: 一种将柔性电路化基板接合到电路化基板（例如印刷电路板）上以使用焊料互连两个基板的选定电路的方法。 将焊膏施加在电路化基板上的导电焊盘和与其相邻的有机润湿材料（例如环氧涂层）上。 柔性基板具有位于柔性基板的电介质内和/或穿过柔性基板的电介质中的孔的导体，位于焊膏上方，并且加热（例如，在烘箱中）。 该糊状物从有机材料中去湿，“起球”并且基本上包围附着在柔性基底导体的桥接部分上的焊料部件（球），从而连接两个基片。 可以使用框架构件，以在焊料构件附接到其之间以及将具有焊接构件的柔性基板与所述下基板上的相应焊膏位置对准时对准柔性基板。

公开(公告)号：US5046955A

公开(公告)日：1991-09-10

申请号：US462263

申请日：1990-01-09

Applicant: Billy E. Olsson

Inventor： Billy E. Olsson

IPC: H01R12/83 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01R12/83 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10477 ,  H05K3/3447 ,  H05K3/368

Abstract: An active connector assembly (10) for use in acting on electrical signals is disclosed. The assembly (10) includes a receptacle (14) for mounting on a printed circuit board (30), a pin header (12) for receiving signals from other data handling systems and a circuit card (16) attached electrically and mechanically along one edge (16a) to contact elements (26) in the pin header (12) and having an opposing edge (16b) for insertion into the receptacle (14) and electrical engagement with contact elements (28) therein.

Abstract translation: 公开了一种用于作用于电信号的有源连接器组件（10）。 组件（10）包括用于安装在印刷电路板（30）上的插座（14），用于接收来自其它数据处理系统的信号的引脚（12）和沿着一个边缘电和机械地附接的电路卡 （16a）连接到所述销钉头（12）中的元件（26）并且具有用于插入所述插座（14）的相对边缘（16b）并与其中的接触元件（28）电接合。

公开(公告)号：US5012387A

公开(公告)日：1991-04-30

申请号：US339680

申请日：1989-04-18

Applicant: Hans Ohlenburger

Inventor： Hans Ohlenburger

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K7/20

CPC classification number: H05K1/09 ,  H05K1/0206 ,  H05K2201/0338 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/10946 ,  H05K2201/10969 ,  H05K2203/0723 ,  H05K3/244 ,  H05K3/403 ,  H05K3/42

Abstract: To provide heat dissipation from components mounted on a printed circuit board, a copper layer is applied to a printed circuit board. A layer of pure aluminum is applied to this copper layer by electroplating. The printed circuit board is coated on both sides with copper and pure aluminum layers. The components are mounted on one of the copper and pure aluminum layers. The printed circuit board has bores in the regions of the components. The copper and pure aluminum layers extend over the inner walls of these bores, whereby communication is established between the copper and pure aluminum layer in contact with the components and the copper and aluminum layer on the opposite side of the printed circuit board. The pure aluminum layer applied by electroplating is mechanically machined in the region of the components to achieve a planar surface. Areas are left open in the copper and pure aluminum layer. Soldering contacts and strip conductors are arranged provided on the printed circuit board within these left-open areas.

Abstract translation: 为了从安装在印刷电路板上的组件提供散热，铜层被施加到印刷电路板上。 通过电镀将一层纯铝施加到该铜层上。 印刷电路板的两面涂有铜和纯铝层。 组件安装在铜和纯铝层之一上。 印刷电路板在部件的区域中具有孔。 铜和纯铝层在这些孔的内壁上延伸，由此在与元件相接触的铜和纯铝层之间建立通信，并且在印刷电路板的相对侧上形成铜和铝层。 通过电镀施加的纯铝层在组件的区域中机械加工以实现平坦表面。 区域在铜和纯铝层中保持开放。 焊接触点和带状导体布置在这些左开口区域内的印刷电路板上。

公开(公告)号：US4950527A

公开(公告)日：1990-08-21

申请号：US282949

申请日：1988-12-05

Applicant: Akira Yamada

Inventor： Akira Yamada

IPC: H05K1/02 ,  H05K3/36 ,  B32B9/00

CPC classification number: H05K3/363 ,  H05K1/0201 ,  H05K1/0206 ,  H05K1/0212 ,  H05K2201/062 ,  H05K2201/09172 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2203/0195 ,  H05K2203/0415 ,  Y10S428/901 ,  Y10T428/24777 ,  Y10T428/24917

Abstract: A structure of joining two printed circuit boards with solder. A reserve solder layer is applied on a pattern of joint leads of the printed circuit on a base plate of the first board. A similar pattern of high thermal conductivity to the pattern of joint leads of the second printed circuit board is formed on the opposite or back surface of the base plate thereof in almost or exact coincidence with the latter. To join the first and second boards, the latter is turned upside down and then its joint lead pattern is put on the solder layer in registry with that of the first board. And it is at a point on each patch of the thermal conductivity pattern that heat is then applied thereto to obtain the structure between the joint leads of the two printed circuit boards.

公开(公告)号：US4788767A

公开(公告)日：1988-12-06

申请号：US24491

申请日：1987-03-11

Applicant: Kishor V. Desai ,  Kohn Harold

Inventor： Kishor V. Desai ,  Kohn Harold

IPC: H01L23/50 ,  H01L21/98 ,  H01L23/32 ,  H01L23/498 ,  H01L23/538 ,  H01R43/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3436 ,  H05K3/363 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/207 ,  H01L2924/30107 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10704 ,  H05K2203/0415 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: A method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package, such that the flexible film of the carrier is supported substantially in a plane above the surface of the second level electronic package. The method comprises positioning preformed spacers embedded in a dissolvable polysulfone foam holder between the outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding (matching) bonding pads on the second level electronic package. Each of the preformed spacers may comprise, for example, a solder cylinder with a copper core. The preformed spacers may be bonded to the outer lead bonding pads on the chip carrier, and to the matching bonding pads on the second level electronic package, by reflowing the solder of the spacers using, for example, a conventional solder reflow oven. Then, the holder is dissolved, and washed away, in a conventional vapor degreaser using, for example, methylene chloride, to leave the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.