公开(公告)号：US11749590B2

公开(公告)日：2023-09-05

申请号：US17123668

申请日：2020-12-16

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tatsuya Koike

IPC: H01L23/528 ,  H01L23/498 ,  H05K3/34 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H05K1/115 ,  H05K3/34 ,  H05K3/3452 ,  H05K3/4015 ,  H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K2201/095 ,  H05K2201/098 ,  H05K2203/02 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end, an upper end and a narrowed part between the lower end and the upper end, and a plurality of solders each of which has a melting point lower than the terminals and covers a surface of the corresponding terminal.

公开(公告)号：US20180270952A1

公开(公告)日：2018-09-20

申请号：US15694962

申请日：2017-09-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroshi OTA ,  Daigo SUZUKI ,  Yasutomo SAKURAI ,  Hitoshi SAITOU

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/1283 ,  H05K3/4046 ,  H05K3/4053 ,  H05K3/42 ,  H05K2201/0305 ,  H05K2201/09572 ,  H05K2201/098 ,  H05K2201/09854 ,  H05K2201/10303

Abstract: A module includes a substrate, a first wiring, a second wiring, and an interlayer connection section. The substrate includes a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and an inner surface of a hole extending between the first surface and the second surface. The first wiring is provided on the first surface. The second wiring is provided on the second surface. The interlayer connection section includes a first conductor provided on the inner edge, connected to the first wiring and the second wiring, thinner than the first wiring, and thinner than the second wiring, and a second conductor disposed in the hole and electrically connected to the first conductor.

公开(公告)号：US10079158B2

公开(公告)日：2018-09-18

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K7/00 ,  H01P3/08 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H05K1/00 ,  H05K1/11 ,  H01P3/00 ,  H01P3/02 ,  H01P5/02 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

公开(公告)号：US20180153034A1

公开(公告)日：2018-05-31

申请号：US15864301

申请日：2018-01-08

Applicant: Toppan Forms Co., Ltd.

Inventor： Kumi Hirose ,  Takuya Sekiguchi ,  Nariaki Nawa

IPC: H05K1/09 ,  H05K1/02 ,  G06F3/044 ,  G06F3/041 ,  H05K3/12

CPC classification number: H05K1/092 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/0225 ,  H05K1/0274 ,  H05K3/1275 ,  H05K2201/032 ,  H05K2201/09681 ,  H05K2201/098

Abstract: A wiring board includes: thin silver wires formed on a substrate by a printing method, in which the thin silver wires are configured so that the width thereof in a cross-section in a direction perpendicular to a wire length direction thereof is 20 μm or less, a top thereof has a smaller width than that of a contact portion that comes into contact with the substrate, and a volume resistivity of the thin silver wire is 15 μΩ·cm or less.

公开(公告)号：US09980374B2

公开(公告)日：2018-05-22

申请号：US15033836

申请日：2014-10-24

Applicant: INGENICO GROUP

Inventor： Stephane Pavageau ,  Xavier Lambert

IPC: H05K7/00 ,  H05K1/02 ,  G06K7/00 ,  G06F21/86 ,  B23K1/00 ,  H05K3/10 ,  H05K3/34 ,  H05K3/12 ,  H05K3/14 ,  H05K3/24 ,  B23K101/42

CPC classification number: H05K1/0284 ,  B23K1/0016 ,  B23K2101/42 ,  G06F21/86 ,  G06K7/0091 ,  H05K1/0275 ,  H05K3/10 ,  H05K3/1241 ,  H05K3/1275 ,  H05K3/143 ,  H05K3/245 ,  H05K3/34 ,  H05K2201/09409 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/10204 ,  H05K2203/0551

Abstract: A support is provided for fabrication of an electronic device. The support includes at least one component to be protected and at least one three-dimensional element of a height at least equal to a height of the electronic component. The three-dimensional element is disposed laterally opposite the at least one component to be protected. The three-dimensional element is chiefly constituted of a permanent assembling material.

公开(公告)号：US09980371B2

公开(公告)日：2018-05-22

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H05K3/02 ,  H05K3/18

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

公开(公告)号：US09913383B2

公开(公告)日：2018-03-06

申请号：US15594778

申请日：2017-05-15

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Mi Bae ,  Soon Gyu Kwon ,  Sang Hwa Kim ,  Sang Young Lee ,  Jin Hak Lee ,  Han Su Lee ,  Dong Hun Jeong ,  In Ho Jeong ,  Dae Young Choi ,  Jung Ho Hwang

IPC: H05K1/09 ,  H05K3/24 ,  H05K3/18 ,  C25D5/48 ,  C25D5/02 ,  C25D3/38 ,  C25D3/48 ,  C25D7/12

CPC classification number: H05K1/11 ,  C25D3/38 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/09 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/1184

Abstract: A printed circuit board includes: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au), wherein a width of a bottom surface of the surface treatment layer is narrower than a width of a top surface of the plating seed layer, wherein the bottom surface of the surface treatment layer includes: a first portion contacted with the circuit pattern layer; and a second portion non contacted with the circuit pattern layer, and wherein a width of a top surface of the circuit pattern layer is narrower than a width of a bottom surface of the circuit pattern layer.

公开(公告)号：US20170135223A1

公开(公告)日：2017-05-11

申请号：US15406132

申请日：2017-01-13

Applicant: LG INNOTEK CO., LTD.

Inventor： Jung Ho Hwang ,  Han Su Lee ,  Dae Young Choi ,  Soon Gyu Kwon ,  Dong Hun Jeong ,  In Ho Jeong ,  Kil Dong Son ,  Sang Hwa Kim ,  Sang Young Lee ,  Jae Hoon Jeon ,  Jin Hak Lee ,  Yun Mi Bae

IPC: H05K3/18 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K3/188 ,  H05K1/0298 ,  H05K1/09 ,  H05K3/002 ,  H05K3/108 ,  H05K3/244 ,  H05K2201/0347 ,  H05K2201/098 ,  H05K2203/0548 ,  H05K2203/0588 ,  H05K2203/0723 ,  H05K2203/1184

Abstract: Disclosed are a printed circuit board and a method of manufacturing the printed circuit board. The printed circuit board includes an insulating layer, and a circuit pattern formed on the insulating layer, wherein the circuit pattern includes a first circuit pattern formed on the insulating layer and including a corner portion of an upper portion which has a predetermined curvature and a second circuit pattern formed on the first circuit pattern and configured to cover an upper surface of the first circuit pattern including the corner portion.

公开(公告)号：US09648732B2

公开(公告)日：2017-05-09

申请号：US14455052

申请日：2014-08-08

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Youko Nakamura ,  Norihiro Nashida

IPC: H05K1/18 ,  H01L23/28 ,  H05K1/02 ,  H01L31/048 ,  H01L33/56 ,  H01L23/12 ,  H01L33/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/00 ,  H05K1/11 ,  H05K7/00 ,  H01L23/29 ,  H01L25/07

CPC classification number: H05K1/0296 ,  H01L21/56 ,  H01L21/563 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/01 ,  H01L25/072 ,  H01L31/048 ,  H01L33/52 ,  H01L33/56 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/115 ,  H05K1/185 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/098 ,  H01L2924/00

Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.

公开(公告)号：US09572256B2

公开(公告)日：2017-02-14

申请号：US14633864

申请日：2015-02-27

Applicant: IBIDEN CO., LTD.

Inventor： Kazuhiro Yoshikawa ,  Takashi Kariya

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H01L23/00 ,  H05K3/28 ,  H05K3/40 ,  H05K1/14 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/144 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/042 ,  H05K2201/068 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/10977 ,  H05K2201/2072 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/0405 ,  H05K2203/0594 ,  H05K2203/0597 ,  H05K2203/1184 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed wiring board includes an uppermost insulating layer, first pads positioned to mount an IC chip on the insulating layer, second pads positioned to mount a second printed wiring board on the insulating layer, metal posts formed on the second pads, respectively, such that the metal posts mount the second board over the chip, and a solder resist layer formed on the uppermost insulating layer and having first and second openings such that the first openings exposes the first pads and that the second openings exposes the second pads, respectively. The metal posts are formed such that each of the metal posts has a diameter which is smaller than a diameter of each of the second opening portions, and the second opening portions are formed such that the diameter of each of the second opening portions is smaller than a diameter of each of the second pads.

Abstract translation: 印刷布线板包括最上层的绝缘层，位于绝缘层上的IC芯片安装的第一焊盘，位于绝缘层上的第二印刷电路板安装的第二焊盘，分别形成在第二焊盘上的金属柱，使得 金属柱将第二板安装在芯片上，以及形成在最上层绝缘层上并具有第一和第二开口的阻焊层，使得第一开口暴露第一焊盘，并且第二开口分别暴露第二焊盘。 金属柱形成为使得每个金属柱的直径小于每个第二开口部的直径，并且第二开口部形成为使得每个第二开口部的直径小于 每个第二垫的直径。