公开(公告)号：US08395054B2

公开(公告)日：2013-03-12

申请号：US12616891

申请日：2009-11-12

Applicant: Takashi Kariya ,  Daiki Komatsu

Inventor： Takashi Kariya ,  Daiki Komatsu

IPC: H05K1/16

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5387 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4608 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/055 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/063 ,  H01L2224/05599

Abstract: To provide a substrate for mounting a semiconductor element, in which fine-pitch wiring layers are formed to allow a semiconductor element to be mounted, while heat generated in the semiconductor element will not result in a decrease in reliability. Semiconductor-element mounting substrate sandwiches low-thermal-expansion substrate with upper interlayer resin layer and lower interlayer resin layer, and conductive circuit of organic substrate and first conductive circuit of low-thermal-expansion substrate are connected by via conductor formed in interlayer resin layer. Therefore, low-thermal-expansion substrate for mounting semiconductor element may be connected to organic substrate that is connected to outside substrates, without arranging an organic substrate and resin layers on the lower surface of low-thermal-expansion substrate, where impact from the thermal history of semiconductor element is notable.

Abstract translation: 为了提供用于安装半导体元件的基板，其中形成微细间距布线层以允许安装半导体元件，同时在半导体元件中产生的热量不会导致可靠性降低。 半导体元件安装基板将具有上层间树脂层和下层间树脂层的低热膨胀基板夹持，有机基板的导电电路和低热膨胀基板的第一导电电路通过在层间树脂层中形成的通孔导体连接 。 因此，用于安装半导体元件的低热膨胀基板可以连接到与外部基板连接的有机基板，而不在低热膨胀基板的下表面上布置有机基板和树脂层，其中来自热 半导体元件的历史是值得注意的。

公开(公告)号：US08389870B2

公开(公告)日：2013-03-05

申请号：US12720386

申请日：2010-03-09

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K1/11

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

公开(公告)号：US08383948B2

公开(公告)日：2013-02-26

申请号：US12794106

申请日：2010-06-04

Applicant: Masakazu Aoyama ,  Teruyuki Ishihara ,  Noboru Shibita

Inventor： Masakazu Aoyama ,  Teruyuki Ishihara ,  Noboru Shibita

IPC: H05K1/00

CPC classification number: H05K3/4069 ,  H05K3/4644 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1453 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A flex-rigid wiring board includes a flexible substrate having a first surface and a second surface on the opposite side of the first surface, a first conductive pattern formed on the first surface of the flexible substrate, a second conductive pattern formed on the second surface of the flexible substrate, and a conductor made of a conductive paste and formed in a first hole penetrating through the flexible substrate such that the first conductive pattern and the second conductive pattern are electrically connected to each other.

Abstract translation: 挠性刚性布线板包括柔性基板，其具有在第一表面的相对侧上的第一表面和第二表面，形成在柔性基板的第一表面上的第一导电图案，形成在第二表面上的第二导电图案 柔性基板和由导电膏制成的导体，并且形成在穿过柔性基板的第一孔中，使得第一导电图案和第二导电图案彼此电连接。

公开(公告)号：US08354601B2

公开(公告)日：2013-01-15

申请号：US12798217

申请日：2010-03-31

Applicant: James V. Russell

Inventor： James V. Russell

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K1/0222 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/09809 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method and a structure for a coaxial via that extend along the entire length of a signal via in a printed circuit board. Signal integrity is improved by providing ground shield for the entire length of the coaxial via. The ground shielding can be implemented by either providing ground cage vias around a signal via and routing a trace to the signal via on a built up layer or by providing a semi circle ground trench through a build up layer to permit a trace access to the signal via.

Abstract translation: 一种用于沿着印刷电路板中的信号通道的整个长度延伸的同轴通孔的方法和结构。 通过为同轴通孔的整个长度提供接地屏蔽来改善信号完整性。 接地屏蔽可以通过在信号通孔周围提供接地保持架通孔，并将迹线路由到建立层上的信号通道或者通过建立层提供半圆接地沟槽来实现，以允许对信号进行跟踪访问 通过。

公开(公告)号：US20120275124A1

公开(公告)日：2012-11-01

申请号：US13383237

申请日：2010-07-09

Applicant: Rainer Pludra ,  Dietmar Drofenik ,  Johannes Stahr ,  Siegfried Götzinger ,  Liubomir Mareljic

Inventor： Rainer Pludra ,  Dietmar Drofenik ,  Johannes Stahr ,  Siegfried Götzinger ,  Liubomir Mareljic

IPC: H05K3/10 ,  H05K7/06

CPC classification number: H05K1/142 ,  H05K1/115 ,  H05K1/185 ,  H05K1/189 ,  H05K3/225 ,  H05K3/368 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/09163 ,  H05K2201/09845 ,  H05K2203/1461 ,  Y10T29/49155

Abstract: In a method for producing a printed circuit board consisting of at least two printed circuit regions, wherein the printed circuit board regions each comprise at least one conductive layer and/or at least one device or one conductive component, wherein printed circuit board regions (20, 21, 22) to be connected to one another, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a coupling or connection, and wherein, after a coupling or connection of printed circuit board regions (20, 21, 22) to be connected to one another, at least one additional layer or ply of the printed circuit board is arranged or applied over the printed circuit board regions (20, 21, 22) to be connected to one another, it is provided that the additional layer is embodied as a conductive layer (26), which is contact-connected via plated-through holes (23) to conductive layers or devices or components integrated in the printed circuit board regions (20, 21, 22) to be connected to one another, as a result of which a simple and reliable connection or coupling of printed circuit board regions (20, 21, 22) to be connected to one another can be made available.Furthermore, a printed circuit board consisting of a plurality of printed circuit board regions (20, 21, 22) is made available.

Abstract translation: 在制造由至少两个印刷电路区域组成的印刷电路板的方法中，其中印刷电路板区域各自包括至少一个导电层和/或至少一个器件或一个导电部件，其中印刷电路板区域（20 ，21,22）彼此连接，在每种情况下，至少一个彼此直接相邻的侧表面的区域通过联接或连接彼此连接，并且其中在连接或连接印刷后 电路板区域（20,21,22）彼此连接，印刷电路板的至少一个附加层或层被布置或施加在印刷电路板区域（20,21,22）上以被连接到 另一方面，附加层被实施为导电层（26），其通过电镀通孔（23）与导电层或集成在印刷电路板区域中的器件或部件接触连接 ns（20,21,22）彼此连接，结果可以使得要彼此连接的印刷电路板区域（20,21,22）的简单且可靠的连接或耦合可用。 此外，由多个印刷电路板区域（20,21,22）组成的印刷电路板是可用的。

公开(公告)号：US08275223B2

公开(公告)日：2012-09-25

申请号：US12610561

申请日：2009-11-02

Applicant: Dongdong Wang ,  Masataka Ito

Inventor： Dongdong Wang ,  Masataka Ito

IPC: G02B6/12

CPC classification number: G02B6/43 ,  H05K1/0274 ,  H05K3/4644 ,  H05K3/4691 ,  H05K2201/0187 ,  Y10T29/49124 ,  Y10T156/10

Abstract: An opto-electrical hybrid wiring board is formed with a flexible wiring board; a first rigid wiring board and second rigid wiring board connected to each other by the flexible wiring board; a light-emitting element and a light-receiving element, one of which is arranged on the first rigid wiring board and the other on the second rigid wiring board; and a flexible optical waveguide for optically connecting the light-emitting element and the light-receiving element. One end of the flexible wiring board is inserted in and supported by the first rigid wiring board, and the other end is inserted in and supported by the second rigid wiring board; the rigid wiring boards and flexible wiring board are electrically connected to each other by using vias to connect the wiring of the first and second rigid wiring boards and the wiring of the flexible wiring board at the inserted portions.

Abstract translation: 光电混合布线板形成有柔性布线板; 通过柔性布线板相互连接的第一刚性布线板和第二刚性布线板; 发光元件和光接收元件，其中一个布置在第一刚性布线板上，另一个布置在第二刚性布线板上; 以及用于光学连接发光元件和光接收元件的柔性光波导。 柔性布线板的一端插入并由第一刚性布线板支撑，另一端插入第二刚性布线板并由第二刚性布线板支撑; 通过使用通孔将刚性布线板和柔性布线板彼此电连接，以在插入部分连接第一和第二刚性布线板的布线和柔性布线板的布线。

公开(公告)号：US08264847B2

公开(公告)日：2012-09-11

申请号：US12848000

申请日：2010-07-30

Applicant: Jin-Hong An ,  Jae-Soon Kim

Inventor： Jin-Hong An ,  Jae-Soon Kim

IPC: H05K7/02 ,  H05K3/28

CPC classification number: H05K3/284 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/288 ,  H05K2201/0187 ,  H05K2201/0397 ,  H05K2203/1316 ,  H05K2203/1476 ,  H05K2203/162

Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.

Abstract translation: 公开了一种电子电路模块及其制造方法。 在一个实施例中，电子电路模块包括i）其上形成电路的基板，ii）电连接到电路的多个电气装置，以及iii）涂覆在基板上的至少覆盖电气装置的第一模制单元 。 该模块还包括i）测试终端单元，包括多个测试线并被配置为检查电路，其中每个测试线包括电连接到该电路的第一端和从第一模制单元暴露的第二端，以及 其中所述测试线的第二端形成检查单元并且在所述基底上彼此相邻，以及ii）涂覆在所述基底上以覆盖所述测试线的第二端的第二模制单元。

公开(公告)号：US08261435B2

公开(公告)日：2012-09-11

申请号：US12606593

申请日：2009-10-27

Applicant: Hiroyasu Nagata

Inventor： Hiroyasu Nagata

IPC: H05K3/30

CPC classification number: B32B37/025 ,  B32B2038/0092 ,  B32B2309/02 ,  B32B2309/105 ,  B32B2309/12 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H05K1/0231 ,  H05K1/0269 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10712 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T156/11 ,  Y10T156/1195

Abstract: A method for manufacturing printed wiring board including preparing an electronic component having first and second surfaces and electrode on the first surface, forming in an adhesive tape a mark, mounting based on the mark the component on the tape such that the second surface faces the adhesive of the tape, forming another mark on insulative substrate having first and second surfaces, forming in the substrate an opening larger than the component, mounting based on the marks the substrate on the tape such that the component is in the opening of the substrate, fixing the component to the substrate using resin, forming an insulation layer on the first surface of the substrate where the component is accommodated, removing the tape, forming in the layer an opening reaching the electrode, forming a conductive circuit on the layer, and forming in the opening of the layer a via connected to the electrode.

Abstract translation: 一种制造印刷线路板的方法，包括制备具有第一和第二表面的电子部件和在第一表面上的电极，在胶带上形成标记，基于将该部件标记在带上以使得第二表面面向粘合剂 的带，在具有第一和第二表面的绝缘基板上形成另一个标记，在基板上形成比部件大的开口，基于将基板标记在带上的安装，使得部件在基板的开口中，固定 使用树脂的基板上的部件，在容纳部件的基板的第一表面上形成绝缘层，去除带，在该层中形成到达电极的开口，在该层上形成导电电路，并形成 打开连接到电极的层a通孔。

公开(公告)号：US20120180312A1

公开(公告)日：2012-07-19

申请号：US13430233

申请日：2012-03-26

Applicant: Zhichao Zhang ,  Kemal Aygun ,  Guizhen Zheng

Inventor： Zhichao Zhang ,  Kemal Aygun ,  Guizhen Zheng

IPC: H05K3/10

CPC classification number: H05K1/024 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09581 ,  Y10T29/49155

Abstract: In integrated circuit packages, core vias are created to provide electrical connections between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods for forming a via in a packaging substrate and packaging substrates having core vias formed in the core substrate material. Methods for forma a core via in a packaging substrate in which a first hole is created through the core substrate and filled with a low permittivity filler material. A second co-axially aligned hole is then created in the low permittivity filler material wherein the second hole is smaller in diameter than the first hole. The second hole is then filled with conducting material to provide a conducting via through the core substrate material.

Abstract translation: 在集成电路封装中，形成核心通孔以在芯基板材料的一个面上的电路与芯基板材料的相对面上的电路之间提供电连接。 提供了在封装基板中形成通孔的方法以及在芯基板材料中形成有芯通孔的封装基板。 在包装基材中形成芯通孔的方法，其中通过芯基板产生第一孔并填充低介电常数的填充材料。 然后在低介电常数填充材料中产生第二同轴对准的孔，其中第二孔的直径小于第一孔。 然后用导电材料填充第二孔，以通过芯基板材料提供导电通孔。

公开(公告)号：US08222537B2

公开(公告)日：2012-07-17

申请号：US12483223

申请日：2009-06-11

Applicant: George Dudnikov, Jr. ,  Franz Gisin

Inventor： George Dudnikov, Jr. ,  Franz Gisin

IPC: H05K1/11

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过PCB堆叠穿过导电层，电介质层和通过电镀抗蚀剂钻穿孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。