公开(公告)号：US09596764B2

公开(公告)日：2017-03-14

申请号：US14577333

申请日：2014-12-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Naoki Gouchi

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0287 ,  H05K1/0292 ,  H05K1/0293 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/24 ,  H05K3/4007 ,  H05K3/4092 ,  H05K3/4632 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10007 ,  H05K2201/10159 ,  H05K2201/10984 ,  H05K2201/2072 ,  H05K2203/0271 ,  H05K2203/063 ,  H05K2203/08

Abstract: To prevent decrease of the bonding strength of an electronic component and a multilayer substrate, an electronic component-embedded module may include an electronic component having a plurality of pads and a multilayer substrate which includes a plurality of resin layers and a cavity for containing the electronic component. The multilayer substrate may include a first resin layer having a plurality of first pattern conductors and a space, and a second resin layer having a second pattern conductor and a plurality of third pattern conductors. The plurality of third pattern conductors may be in conduction with either of the first pattern conductors or the pads, with the second resin layer being placed over the first resin layer. The second pattern conductor may be arranged around a first pad with a gap, and the second resin layer is present between the second pattern conductor and at least one of the first pads.

Abstract translation: 为了防止电子部件和多层基板的接合强度的降低，电子部件嵌入式模块可以包括具有多个焊盘的电子部件和包括多个树脂层的多层基板和用于容纳电子部件的空腔 零件。 多层基板可以包括具有多个第一图案导体和空间的第一树脂层和具有第二图案导体和多个第三图案导体的第二树脂层。 多个第三图案导体可以与第一图案导体或垫中的任一个导通，其中第二树脂层被放置在第一树脂层上。 第二图案导体可以布置在具有间隙的第一衬垫周围，并且第二树脂层存在于第二图案导体和至少一个第一衬垫之间。

公开(公告)号：US09578760B2

公开(公告)日：2017-02-21

申请号：US14721973

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojae Bang ,  Dogeun Kim ,  Hongkyun Kim ,  Youngbok Jeon

IPC: H05K1/14 ,  H05K5/00 ,  G06K7/00 ,  H01R12/57 ,  H01R12/50 ,  H05K1/11 ,  H01R13/00 ,  H05K3/10 ,  H05K3/30 ,  H05K7/02 ,  H05K13/00 ,  G06F1/18 ,  H05K1/18 ,  H01R27/00 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K5/0026 ,  G06F1/18 ,  G06F1/185 ,  G06K7/0047 ,  H01R12/57 ,  H01R12/721 ,  H01R13/00 ,  H01R23/70 ,  H01R27/00 ,  H05K1/0295 ,  H05K1/11 ,  H05K1/117 ,  H05K1/181 ,  H05K3/10 ,  H05K3/303 ,  H05K3/3405 ,  H05K7/02 ,  H05K13/00 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10446 ,  Y10S439/946 ,  Y10S439/951 ,  Y10T29/49124 ,  Y10T29/49147

Abstract: Example embodiments are directed to circuit boards, connectors, cases, circuit board assemblies, case assemblies, devices and methods of manufacturing the same, which are common to at least two different form factors. In an example embodiment, the SSD includes a circuit board that is smaller than a case, and the circuit board is secured to the bottom surface of the case by the securing element. The securing element is spaced apart from edges of the case to allow using a circuit board that is smaller than the case.

Abstract translation: 示例性实施例涉及电路板，连接器，外壳，电路板组件，壳体组件，其制造方法及其制造方法，这对于至少两种不同的形状因子是共同的。 在示例性实施例中，SSD包括小于壳体的电路板，并且电路板通过固定元件固定到壳体的底表面。 固定元件与壳体的边缘间隔开，以允许使用小于壳体的电路板。

公开(公告)号：US09565756B2

公开(公告)日：2017-02-07

申请号：US13853338

申请日：2013-03-29

Applicant: IBIDEN CO., LTD.

Inventor： Makoto Terui ,  Daiki Komatsu ,  Masatoshi Kunieda

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K1/0298 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H05K3/3436 ,  H05K3/4644 ,  H05K3/4694 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.

Abstract translation: 布线板包括第一绝缘层，形成在第一绝缘层上的第一导电图案，形成在第一绝缘层上的第二绝缘层和第一导电图案，并具有开口部分，布置结构容纳在第一绝缘层的开口部分中 第二绝缘层，并且在绝缘层上包括绝缘层和导电图案，形成在第二绝缘层上的第二导电图案; 以及形成在所述第二绝缘层中并连接所述第一导电图案中的一个和所述第二导电图案中的一个的通孔导体。

公开(公告)号：US20160351543A1

公开(公告)日：2016-12-01

申请号：US15117345

申请日：2015-01-28

Applicant: LG INNOTEK CO., LTD.

Inventor： Sung Wuk RYU ,  Dong Sun KIM ,  Ji Haeng LEE ,  Sang Hyuck NAM

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15701 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/144 ,  H05K1/186 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: A printed circuit board according to the present invention comprises: an insulating substrate; a plurality of pads formed on the upper surface of the insulating substrate; a protective layer which comprises an opening part for exposing the upper surfaces of the plurality of pads, and is formed on the insulating substrate; and a metal bump which is formed on the first pad and the second pad in the plurality of pads, and projects above the surface of the protective layer, and, here, the first pad is formed to the left of the central upper part of the insulating substrate, while the second pad is formed to the right of the central upper part of the insulating substrate.

Abstract translation: 根据本发明的印刷电路板包括：绝缘基板; 形成在所述绝缘基板的上表面上的多个焊盘; 保护层，其包括用于暴露所述多个焊盘的上表面的开口部，并且形成在所述绝缘基板上; 以及金属凸块，其形成在所述多个焊盘中的所述第一焊盘和所述第二焊盘上，并且在所述保护层的表面上方突出，并且在这里，所述第一焊盘形成在所述保护层的中央上部的左侧 绝缘基板，而第二焊盘形成在绝缘基板的中央上部的右侧。

公开(公告)号：US09504138B2

公开(公告)日：2016-11-22

申请号：US14446289

申请日：2014-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Kim ,  Jin-Hyuk Lee

IPC: H05K1/02 ,  H01L23/52 ,  H01L23/36 ,  H05K1/18

CPC classification number: H05K1/0207 ,  H01L23/36 ,  H01L23/52 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10371 ,  H05K2201/10416 ,  H01L2924/00

Abstract: Embodiments of the inventive concept include a semiconductor device having a circuit board including a first outer layer, a contact region in the first outer layer, a second layer formed on an opposite side of the first outer layer, a via-hole, and a plurality of inner layers formed to be stacked between the first layer and the second layer. A case may accommodate the circuit board. The case may have a projection portion that is configured to come in contact with the circuit board in the contact region. The plurality of inner layers may include a ground layer. The first outer layer may be connected to the ground layer through a via-hole. The case may be connected to the ground layer through the first outer layer.

Abstract translation: 本发明构思的实施例包括具有电路板的半导体器件，该电路板包括第一外层，第一外层中的接触区域，形成在第一外层的相对侧上的第二层，通孔和多个 的内层被形成为堆叠在第一层和第二层之间。 一个案例可以容纳电路板。 壳体可以具有突出部分，其被配置为在接触区域中与电路板接触。 多个内层可以包括接地层。 第一外层可以通过通孔连接到接地层。 壳体可以通过第一外层连接到接地层。

公开(公告)号：US20160338190A1

公开(公告)日：2016-11-17

申请号：US15134922

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： PoHao CHANG ,  Chun-Wei CHANG

IPC: H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0213 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/09 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/10159

Abstract: An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB) with a first signal path and a second signal path therein, a first finger disposed on the first signal path, a second finger disposed on the second signal path, a controller disposed on the PCB and coupled to a first memory via the first finger and to a second memory via the second finger, and a damping device disposed on the second signal path. The first and second signal paths share a common segment between the controller and a branch point on the PCB. The damping device is disposed between the second finger and the branch point. The distance between the first finger and the branch point within the first signal path is smaller than the distance between the second finger and the branch point within the second signal path.

Abstract translation: 提供电子设备。 电子设备包括：具有第一信号路径和第二信号路径的印刷电路板（PCB），设置在第一信号路径上的第一手指，设置在第二信号路径上的第二手指，布置在PCB上的控制器 经由第一手指耦合到第一存储器，经由第二手指耦合到第二存储器，以及设置在第二信号路径上的阻​​尼装置。 第一和第二信号路径共享控制器和PCB上的分支点之间的公共段。 阻尼装置设置在第二手指和分支点之间。 第一手指与第一信号路径内的分支点之间的距离小于第二手指与第二信号路径内的分支点之间的距离。

公开(公告)号：US09485854B2

公开(公告)日：2016-11-01

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16 ,  H01P1/26 ,  H01P5/16 ,  H04L25/03

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09462694B2

公开(公告)日：2016-10-04

申请号：US14561768

申请日：2014-12-05

Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.

Inventor： Junrong Yan ,  Weili Wang ,  Li Wang ,  Pradeep Rai ,  Xin Lu ,  Jianbin Gu ,  Peng Lu

IPC: G11C16/02 ,  H05K1/18 ,  H01L25/065

CPC classification number: H05K1/181 ,  H01L25/065 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/181 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/2018 ,  Y02P70/611 ,  Y10T428/24273 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

Abstract translation: 公开了一种半导体器件及其制造方法。 半导体器件包括安装在基板的表面上的诸如控制器管芯的半导体管芯。 间隔层也安装到基底上，其中半导体管芯配合在通过间隔层的第一和第二主要相对表面形成的孔或凹口内。 另外的半导体管芯，例如闪速存储器管芯，可以安装在间隔层顶上。

公开(公告)号：US20160276316A1

公开(公告)日：2016-09-22

申请号：US15168789

申请日：2016-05-31

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  G06F1/18 ,  H05K1/18

CPC classification number: H01L25/0657 ,  G06F1/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Abstract translation: 微电子组件（300）或系统（1500）包括至少一个微电子封装（100），所述微电子封装（100）具有面向上安装在衬底（102）的第一表面（108）上方的微电子元件（130），一个或多个柱 ，140）沿着所述微电子元件正面在第一方向（142）延伸的触点（132）。 在基板的第二表面（110）处露出的端子（1057a）的列（104A，105B，107A，107B）沿第一方向延伸。 具有宽度（152）不大于终端列的最小间距（150）的三分之一倍的中心区域（112）的表面（110）处的第一端子（105）可被配置为承载地址 用于确定可寻址存储器位置的信息。 微电子元件的轴向平面可以与中心区域相交。

公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

Applicant: Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

Abstract translation: 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。