公开(公告)号：US09345143B2

公开(公告)日：2016-05-17

申请号：US14741545

申请日：2015-06-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kotaro Kodani ,  Kentaro Kaneko ,  Kazuhiro Kobayashi

IPC: H05K3/02 ,  H05K3/10 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K3/20

CPC classification number: H05K3/10 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H05K1/113 ,  H05K3/00 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/1184 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.

公开(公告)号：US09338894B2

公开(公告)日：2016-05-10

申请号：US13990823

申请日：2011-12-02

Applicant: Jeroen Van Den Brand ,  Roel Henry Louis Kusters ,  Andreas Heinrich Dietzel

Inventor： Jeroen Van Den Brand ,  Roel Henry Louis Kusters ,  Andreas Heinrich Dietzel

IPC: H05K1/00 ,  H05K3/30 ,  H05K3/32 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H05K1/02 ,  H05K3/12

CPC classification number: H05K3/32 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/76155 ,  H01L2224/76261 ,  H01L2224/766 ,  H01L2224/767 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/82874 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0283 ,  H05K1/189 ,  H05K3/12 ,  H05K3/305 ,  H05K2201/10674 ,  H05K2203/107 ,  H05K2203/1469 ,  H05K2203/1545 ,  H05K2203/175 ,  Y10T29/49133 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A method is presented for assembling a component (30) with a flexible substrate (10), the component having electric contacts (31). The method comprises the steps of placing the component (30) on a first main side (11) of the substrate, applying a machine vision step to estimate a position of the electric contacts, depositing one or more layers (32) of an electrically conductive material or a precursor thereof, said layer extending over an area of the substrate defined by the component to laterally beyond said area, calculating partitioning lines depending on the estimated position of the electric contacts, partitioning the layer into mutually insulated areas (32d) by locally removing material from said layer along said partitioning lines. Also an apparatus is presented that is suitable for carrying out the method.In addition an assembly is present that can be obtained by the method and the apparatus according to the invention.

Abstract translation: 提出了一种用于将组件（30）与柔性基板（10）组装的方法，该部件具有电触点（31）。 该方法包括以下步骤：将组件（30）放置在衬底的第一主侧（11）上，施加机器视觉步骤以估计电触点的位置，沉积导电的一个或多个层（32） 材料或其前体，所述层在由所述部件限定的衬底的区域上延伸到横向超过所述区域，根据所述电触点的估计位置计算划分线，通过局部将所述层划分为相互绝缘的区域（32d） 沿着所述分隔线从所述层去除材料。 还提出了适合于执行该方法的装置。 此外，存在可以通过根据本发明的方法和装置获得的组件。

公开(公告)号：US20160118360A1

公开(公告)日：2016-04-28

申请号：US14990515

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/17 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/66 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/3003 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/1047 ,  H01L2225/1058 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

公开(公告)号：US20160118322A1

公开(公告)日：2016-04-28

申请号：US14837131

申请日：2015-08-27

Applicant: FUJITSU LIMITED

Inventor： Takashi KANDA ,  Shunji BABA

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/00 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/1403 ,  H01L2224/16225 ,  H05K3/4614 ,  H05K3/4694 ,  H05K2201/10674

Abstract: A laminated substrate includes: a core portion; a first wiring portion configured to be stacked on the core portion and to include a first exposed surface formed by exposing at least part of a surface of the first wiring portion; and a second wiring portion configured to be stacked on the first wiring portion, to include a second exposed surface formed by exposing at least part of a surface of the second wiring portion, and to have higher wiring density of conductor than the first wiring portion has, wherein the first exposed surface and the second exposed surface are provided respectively with a first pad and a second pad which are to be connected to electrodes of one semiconductor chip to be mounted on both the first exposed surface and the second exposed surface.

Abstract translation: 层叠基板包括：芯部; 第一布线部，被配置为堆叠在所述芯部上，并且包括通过暴露所述第一布线部的表面的至少一部分而形成的第一暴露表面; 以及第二布线部，其被配置为层叠在所述第一布线部上，以包括通过暴露所述第二布线部的表面的至少一部分而形成的第二暴露表面，并且具有比所述第一布线部具有更高的导体布线密度 其中，所述第一暴露表面和所述第二暴露表面分别设置有要连接到要安装在所述第一暴露表面和所述第二暴露表面上的一个半导体芯片的电极的第一焊盘和第二焊盘。

公开(公告)号：US09324688B2

公开(公告)日：2016-04-26

申请号：US14273485

申请日：2014-05-08

Applicant: SK HYNIX INC.

Inventor： Ki Jun Sung ,  Seung Jee Kim ,  Jong Hyun Nam ,  Sang Yong Lee ,  Young Geun Yoo

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/03 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/09134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01029

Abstract: An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.

Abstract translation: 嵌入式封装包括嵌入在封装衬底中的第一半导体芯片，设置在封装衬底的第一表面上的第二半导体芯片和设置在封装衬底的第一表面上以及位于封装衬底的侧壁之间的一组外部连接接头 第二半导体芯片和嵌入式封装的边缘。 还提供了相关的存储卡和相关的电子系统。

公开(公告)号：US09324678B2

公开(公告)日：2016-04-26

申请号：US13996498

申请日：2011-12-20

Applicant: Sanka Ganesan ,  Ram S. Viswanath

Inventor： Sanka Ganesan ,  Ram S. Viswanath

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00 ,  H01R12/62 ,  H05K3/36 ,  H01L23/498 ,  H01B7/04 ,  H05K1/14

CPC classification number: H01R12/79 ,  H01B7/04 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R12/62 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H01L2224/0401

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract translation: 介绍了一种集成电路封装。 在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。 集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。 柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

公开(公告)号：US20160113115A1

公开(公告)日：2016-04-21

申请号：US14793384

申请日：2015-07-07

Applicant: HEUNG KYU KWON ,  KYOUNG MOOK LIM

Inventor： HEUNG KYU KWON ,  KYOUNG MOOK LIM

IPC: H05K1/18 ,  G06F1/16 ,  H05K1/02 ,  G01R31/28 ,  H05K5/00 ,  H05K1/11

CPC classification number: H05K1/181 ,  G01R31/2884 ,  G06F1/1613 ,  G06F1/1637 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0215 ,  H05K1/0268 ,  H05K1/112 ,  H05K2201/10159 ,  H05K2201/10371 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

Abstract translation: 封装SoP模块的系统包括具有第一侧和相对的第二侧的印刷电路板（PCB），附接到第一侧的第一IC，附接到第二侧的第二IC。 PCB还提供用于连接第一IC和第二IC的电气路径。 当SoP处于系统级状态时，第二个IC连接到PCB的导体也允许第一个IC的电气测试。

公开(公告)号：US09320148B2

公开(公告)日：2016-04-19

申请号：US13431091

申请日：2012-03-27

Applicant: Yukinobu Mikado ,  Shunsuke Sakai ,  Hirofumi Futamura

Inventor： Yukinobu Mikado ,  Shunsuke Sakai ,  Hirofumi Futamura

IPC: H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H05K1/185 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2203/0191 ,  H05K2203/1469 ,  H01L2924/00

Abstract: A printed wiring board includes a core substrate having a penetrating hole extending through the core substrate, an electronic component accommodated in the penetrating hole of the core substrate, a filler resin filling clearance between the component and the core substrate, a first resin insulation layer formed on the component and a first surface of the core substrate, and a second resin insulation layer formed on the component and a second surface of the core substrate on the opposite side of the first surface of the core substrate. The filler resin has elastic modulus which is set to be lower than 0.2 Gpa and thermal expansion coefficient which is set to be higher than 100 ppm and lower than 200 ppm, and the core substrate has elastic modulus which is set to be higher than 30 Gpa, and thermal expansion coefficient which is set to be lower than 10 ppm.

Abstract translation: 印刷电路板包括具有延伸穿过芯基板的穿透孔的芯基板，容纳在芯基板的贯通孔中的电子部件，部件和芯基板之间的填充树脂填充间隙，形成第一树脂绝缘层 在芯基板的第一表面和与芯基板的第一表面相反的一侧上形成的第二树脂绝缘层和芯基板的第二表面上。 填充树脂的弹性模量设定为低于0.2Gpa，热膨胀系数设定为高于100ppm且低于200ppm，芯基材的弹性模量设定为高于30Gpa ，热膨胀系数设定为低于10ppm。

公开(公告)号：US09287246B2

公开(公告)日：2016-03-15

申请号：US14560859

申请日：2014-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H05K1/02 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5382 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08225 ,  H01L2224/09051 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81395 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.

公开(公告)号：US09287205B2

公开(公告)日：2016-03-15

申请号：US14693995

申请日：2015-04-23

Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.

Inventor： Lei Shi ,  Yujuan Tao

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/50 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L21/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.