公开(公告)号：US06674338B2

公开(公告)日：2004-01-06

申请号：US10342803

申请日：2003-01-15

Applicant: Istvan Novak

Inventor： Istvan Novak

IPC: H03H738

CPC classification number: H05K1/0231 ,  H05K1/0234 ,  H05K1/113 ,  H05K1/167 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10446 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res. The mounted resistance Rm of each of the n capacitors includes an electrical resistance of the corresponding electrical resistance element. The electrical power distribution structure achieves an electrical impedance Z at the resonant frequency fm-res of the capacitors. The mounted resistance Rm of each of the n capacitors is substantially equal to (n·Z). The mounted inductance Lm of each of discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n capacitors is less than or equal to (0.2·n·&mgr;0·h), where &mgr;0 is the permeability of free space, and h is a distance between the planar conductors.

Abstract translation: 通过电耦合多个旁路电容器和在平面导体之间串联的相应的电阻元件来实现电力分配结构的平行平面导体之间的电阻抗的期望值的装置和方法。 该方法包括基于仿真结果的旁路电容器选择标准和电阻确定标准。 通过这些方法之一产生的示例性配电结构包括一对由电介质层分开的平行平面导体，n个分立的电容器和n个电阻元件，其中n≥2。 n个分立电阻元件中的每一个与平面导体之间的n个分立电容器中的相应一个耦合。 n个电容器具有基本相同的电容C，安装电阻Rm，安装电感Lm和安装的谐振频率fm-res。 n个电容器中的每一个的安装电阻Rm包括相应的电阻元件的电阻。 电力分配结构在电容器的谐振频率fm-res处实现电阻抗Z。 n个电容器中的每一个的安装电阻Rm基本上等于（n.Z）。 每个离散电容器的安装电感Lm和n个电阻元件，其中n> = 2。 n个电容器中的每一个小于或等于（0.2.n.mu0.h），其中mu0是自由空间的磁导率，h是平面导体之间的距离。

公开(公告)号：US20030222282A1

公开(公告)日：2003-12-04

申请号：US10426930

申请日：2003-04-29

Inventor： Joseph C. Fjelstad ,  Para K. Segaram ,  Belgacem Haba

IPC: H01L031/0336

CPC classification number: H05K1/147 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0228 ,  H05K1/0237 ,  H05K3/222 ,  H05K2201/10356 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract translation: 一种直接连接信号系统，包括印刷电路板和布置在印刷电路板上的第一和第二集成电路封装。 多个电信号导体在悬挂在印刷电路板上的第一和第二集成电路封装之间延伸。

公开(公告)号：US20030145460A1

公开(公告)日：2003-08-07

申请号：US10067244

申请日：2002-02-07

Inventor： Rebecca A. Jessep ,  David W. Boggs ,  Carolyn McCormick ,  John H. Dungan ,  Daryl A. Sato

IPC: H01L023/52 ,  H05K003/30

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/1319 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/145 ,  H05K3/303 ,  H05K3/308 ,  H05K2201/09809 ,  H05K2201/10022 ,  H05K2201/10303 ,  H05K2201/1053 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10734 ,  H05K2201/10871 ,  H05K2201/2036 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Standoff arrangements to control distance and provide electrical function.

Abstract translation: 隔离布置来控制距离并提供电气功能

公开(公告)号：US06535396B1

公开(公告)日：2003-03-18

申请号：US09560981

申请日：2000-04-28

Applicant: Thomas Alan Degenkolb ,  Darrel Eugene Peugh ,  Bruce Alan Myers

Inventor： Thomas Alan Degenkolb ,  Darrel Eugene Peugh ,  Bruce Alan Myers

IPC: H01R900

CPC classification number: H01L25/162 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01R12/58 ,  H05K1/0263 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/202 ,  H05K3/4084 ,  H05K7/1441 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0397 ,  H05K2201/10272 ,  H05K2201/1053 ,  H01L2924/00014

Abstract: A combination circuit board (12) and segmented bus structure (54) defines a composite circuit board/bus assembly (52) upon which an electrical circuit may be assembled. The various segments (54a-54f) of bus structure (54) may be variously configured to achieve one or more assembly, performance, testing, and/or reliability goals. For example, one bus segment configuration provides integral connector tabs (54a and 54e) for mechanical and/or electrical connection to interconnecting wires or electrical terminals of one or more external devices. Another bus segment configuration (54d) provides for mechanical and high current electrical interconnections between one or more bus segments (54a-54f) and one or more electrical components (16, 18, 20) and/or conductive film patterns(64) formed on top surface (12b) of the circuit board (12). Still another bus segment configuration provides integral tabs (54b and 54c) for electrical connection to and mechanical attachment of electrical components (16, 18, 20) from one or more of such tabs (54b and 54c) extending through the circuit board (12) to other such tabs (54b and 54c) or other circuit structures. Yet another bus structure (54f) provides for highly efficient heat sinking capability and/or electrical connection for electrical components (18) mounted either directly to one or more bus segments (54f) and for electrical components (18) mounted to a substrate (68) that is itself mounted directly to one or more bus segments (54f).

Abstract translation: 组合电路板（12）和分段总线结构（54）限定复合电路板/总线组件（52），电路可以在其上组装。 总线结构（54）的各个段（54a-54f）可以被不同地配置成实现一个或多个组件，性能，测试和/或可靠性目标。 例如，一个总线段配置提供一体的连接器接头（54a和54e），用于机械和/或电连接到一个或多个外部设备的互连电线或电气端子。 另一个总线段配置（54d）提供一个或多个总线段（54a-54f）与一个或多个电气部件（16,18,20）和/或形成在其上的导电膜图案（64）之间的机械和高电流电互连 电路板（12）的顶表面（12b）。 另一个总线段构造提供了一体的突片（54b和54c），用于与延伸穿过电路板（12）的一个或多个这样的突片（54b和54c）电连接并机械地附接电气部件（16,18,20） （54b和54c）或其他电路结构。 另一总线结构（54f）为直接安装到一个或多个总线段（54f）和安装到衬底（68f）上的电气部件（18）的电气部件（18）提供了高效的散热能力和/或电连接 ），其本身直接安装在一个或多个总线段（54f）上。

公开(公告)号：US06509646B1

公开(公告)日：2003-01-21

申请号：US09575637

申请日：2000-05-22

Applicant: Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

Inventor： Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

IPC: H01L21302

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K3/321 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: An apparatus for reducing an electrical noise inside a ball grid array package is disclosed. The apparatus mainly comprises a substrate, a plurality of solder balls and a plurality of inside-connected capacitors. The substrate includes a contact layer, a power plane and a ground plane. The plurality of solder balls are fixed on the contact layer. The plurality of inside-connected capacitors are fixed on the contact layer, and a conductive glue is used to electrically connect the capacitors to the power plane and ground plane to reduce the electrical noise between the power plane and ground plane.

Abstract translation: 公开了一种用于减小球栅阵列封装内的电噪声的装置。 该装置主要包括基板，多个焊球和多个内部连接的电容器。 基板包括接触层，电源平面和接地平面。 多个焊球固定在接触层上。 多个内部连接的电容器固定在接触层上，并且使用导电胶将电容器电连接到电源平面和接地平面，以减小电力平面和接地面之间的电气噪声。

公开(公告)号：US20020177333A1

公开(公告)日：2002-11-28

申请号：US09574647

申请日：2000-05-18

Inventor： Schelto van Doorn

IPC: H01R012/00

CPC classification number: H05K1/181 ,  H05K2201/10083 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Apparatus and methods of electrically connecting integrated circuits and transducers are described. In particular, a transducer includes a base mountable on a substrate (e.g., a printed circuit board), and an input/output (I/O) lead configured to contact an I/O lead of an integrated circuit mounted on the substrate. The transducer may be mounted on the substrate to contact the transducer I/O lead to the integrated circuit I/O lead. The transducer I/O lead is configured to electrically connect to the integrated circuit I/O lead independently of any electrically conductive path of the substrate. The direct electrical connection between the transducer and the integrated circuit provides a high-speed communication channel that avoids the parasitic and high-inductance limitations generally associated with conventional metallic printed circuit board traces. At the same time, the transducer is compatible with existing printed circuit board technologies and integrate circuit technologies and, therefore, may be readily integrated into existing computer systems.

Abstract translation: 描述了电连接集成电路和换能器的装置和方法。 特别地，换能器包括可安装在基板（例如印刷电路板）上的基座以及被配置为接触安装在基板上的集成电路的I / O引线的输入/输出（I / O）引线。 传感器可以安装在基板上，以将换能器I / O引导到集成电路I / O引线。 换能器I / O引线被配置为独立于衬底的任何导电路径电连接到集成电路I / O引线。 传感器和集成电路之间的直接电连接提供了高速通信通道，其避免了与常规金属印刷电路板迹线相关的寄生和高电感限制。 同时，传感器与现有的印刷电路板技术兼容，并集成电路技术，因此可以容易地集成到现有的计算机系统中。

公开(公告)号：US06402531B1

公开(公告)日：2002-06-11

申请号：US09166632

申请日：1998-10-05

Applicant: Janos Legrady

Inventor： Janos Legrady

IPC: H01R1200

CPC classification number: H01R4/028 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/1081 ,  Y02P70/611

Abstract: A capillary action enhanced surface mount pin header includes a first flat substrate provided with a predetermined array of plated-through holes having substantially parallel and each having an internal surface defining a first substantially uniform cross section. Pins are provided each of which defines a longitudinal axis and having one end extending through an associated plated-through hole and another end extending to one side of said first substrate. Each pin has an external surface on at least a portion thereof which is received within an associated plated-through hole which defines a second substantially uniform cross section. In the disclosed embodiment, the pins have square or hexagonal cross sections while the plated-through holes have circular cross sections. The first and second cross sections are dissimilar and configured to provide spaced lines of contact and elongate channels substantially parallel to the axes between the internal and external surfaces and adjacent lines of contact, dimensioned to promote capillary action for molten solder at a channel opening on one side of the first substrate to cause the solder to be drawn through the channels towards the opposite side of the first substrate. A second substantially flat substrate is provided for positioning the solder at points substantially aligned with points on the predetermined array and proximate to at least one channel in at least one plated-through hole prior to melting of the solder.

Abstract translation: 毛细管作用增强的表面安装针头头部包括第一平坦基底，该第一平坦基底设置有基本上平行的预定阵列的电镀通孔，每个具有限定第一基本上均匀横截面的内表面。 提供引脚，每个引脚限定纵向轴线，并且其一端延伸穿过相关联的电镀通孔，而另一端延伸到所述第一基板的一侧。 每个销的至少一部分上具有外表面，该外表面被接纳在限定第二基本均匀横截面的相关电镀通孔内。 在所公开的实施例中，销具有方形或六边形横截面，而电镀通孔具有圆形横截面。 第一和第二横截面是不相似的并且构造成提供基本上平行于内表面和外表面和相邻接触线之间的轴线的间隔开的接触线和细长通道，其尺寸被设计成在一个通道开口上促进熔融焊料的毛细作用 使得焊料通过通道朝向第一基板的相对侧被拉出。 提供第二基本上平坦的基底，用于将焊料定位在基本上与预定阵列上的点对准的点处，并且在焊料熔化之前在至少一个电镀通孔中的至少一个通道附近。

公开(公告)号：US06191955B1

公开(公告)日：2001-02-20

申请号：US09010015

申请日：1998-01-21

Applicant: Joe Guillot ,  Michael Quan Dinh ,  Bill Roberts ,  Linda M. McLemore

Inventor： Joe Guillot ,  Michael Quan Dinh ,  Bill Roberts ,  Linda M. McLemore

IPC: H01L23053

CPC classification number: H05K5/0095 ,  H05K1/141 ,  H05K1/18 ,  H05K3/284 ,  H05K3/3447 ,  H05K5/0091 ,  H05K2201/10037 ,  H05K2201/10083 ,  H05K2201/10303 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10689 ,  Y10S257/924 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/4922

Abstract: An electronic module comprises (a) an electrical assembly of electrical components and a cap. The cap surrounds a portion of the electrical assembly of electrical components to form a pocket between a portion of the electrical assembly of electrical components and the cap. The cap has at least one sidewall, each of the at least one sidewalls having an end, one of at least one sidewalls proximately positioned to at least one electrical lead and having at least one notch positioned in the end, the pocket filled with an encapsulant. A process comprises providing a cap and filling the cap with encapsulant, placing an electrical assembly of electrical components in the cap filled with the preselected amount of encapsulant, and allowing the electrical assembly to seat to a proper depth.

Abstract translation: 电子模块包括（a）电气部件和盖子的电气组件。 盖围绕电气部件的电气组件的一部分，以在电气部件的电气组件的一部分和盖之间形成凹穴。 所述盖具有至少一个侧壁，所述至少一个侧壁中的每一个具有端部，至少一个侧壁中的至少一个侧壁中的至少一个侧壁邻近地定位至少一个电引线并且具有位于其末端的至少一个凹口，所述凹穴填充有密封剂 。 一种方法包括提供盖子并用盖子填充盖子，将电气部件的电气组件放置在填充有预选量的密封剂的盖中，并允许电气组件座位到适当的深度。

公开(公告)号：US5981102A

公开(公告)日：1999-11-09

申请号：US26249

申请日：1998-02-19

Applicant: Ford B. Grigg ,  Rickie C. Lake

Inventor： Ford B. Grigg ,  Rickie C. Lake

IPC: H01M2/02 ,  H01M2/10 ,  H01M6/40 ,  H01M10/04 ,  H05K1/18 ,  H05K3/32 ,  H01M6/42 ,  H01M2/24 ,  H05K3/30 ,  H05K7/02

CPC classification number: H01M2/0222 ,  H01M10/0427 ,  H01M2/1038 ,  H01M2/1044 ,  H05K1/181 ,  H05K3/321 ,  H01M6/40 ,  H05K2201/10037 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  Y10T29/49114 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: In accordance with one aspect of the invention, a thin profile battery apparatus comprises at least two thin profile batteries conductively bonded to one another, with one of the batteries including portion which overhangs the other. In one implementation, the batteries comprise button type batteries. In one implementation, the two thin profile batteries are the same size and shape. In accordance with another aspect, a radio frequency communication device comprises a substrate having conductive paths including an antenna. At least one integrated circuit chip is mounted to the substrate and in electrical connection with a first portion of the substrate conductive paths. At least two thin profile batteries conductively bonded in series with and over one another and a second portion of the substrate conductive paths are included. One of the batteries has a portion which overhangs the other and is in electrical connection with a third portion of the substrate conductive paths. In but another aspect, a method of forming a battery powerable apparatus includes providing at least two thin profile batteries over one another. One of the batteries is conductively connected to a first node location formed on a surface of a substrate. The other of the batteries is provided to overhang the one battery and be electrically connected therewith. The overhang of the other battery is conductively connected with a second node location formed on the surface of the substrate.

Abstract translation: 根据本发明的一个方面，一种薄型电池装置包括至少两个导电地彼此结合的薄型电池，其中一个电池包括一部分悬垂在另一个上的部分。 在一个实施方式中，电池包括按钮式电池。 在一个实施方案中，两个薄型电池具有相同的尺寸和形状。 根据另一方面，射频通信设备包括具有包括天线的导电路径的基板。 至少一个集成电路芯片安装到基板并与基板导电路径的第一部分电连接。 至少两个薄型电池与另一个电池串联连接，并且包括基板导电路径的第二部分。 其中一个电池具有一个突出于另一个并与衬底导电路径的第三部分电连接的部分。 在另一方面，形成电池供电装置的方法包括彼此提供至少两个薄型电池。 其中一个电池导电地连接到形成在基板的表面上的第一节点位置。 电池中的另一个设置成突出一个电池并与其电连接。 另一个电池的突出部与形成在基板的表面上的第二节点位置导电连接。

公开(公告)号：US5949135A

公开(公告)日：1999-09-07

申请号：US991485

申请日：1997-12-16

Applicant: Tetsuro Washida ,  Katsunori Ochi

Inventor： Tetsuro Washida ,  Katsunori Ochi

IPC: H01L25/10 ,  H05K1/18 ,  H01L23/02

CPC classification number: H05K1/182 ,  H01L25/105 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1058 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10689

Abstract: A module mounted in relative high density with semiconductor devices is disclosed. The module includes a mounting substrate which has a hole section; a first semiconductor device having bump electrodes which protrude from one principal surface of a package and lead terminals electrically connected to the bump electrodes; a second semiconductor device which also has bump electrodes that can be structurally and electrically coupled with the bump electrodes of the first semiconductor device and where this second semiconductor device is able to be located in the hole section of the mounting substrate, and where the first semiconductor device is able to be supported on the mounting substrate through the lead terminals; and where the bump electrodes of both semiconductor devices are electrically connected to each other.

Abstract translation: 公开了一种以半导体器件相对高密度安装的模块。 该模块包括具有孔部的安装基板; 第一半导体器件具有从封装的一个主表面突出的凸起电极和电连接到凸块电极的引线端子; 第二半导体器件还具有可以与第一半导体器件的凸起电极结构和电耦合的凸起电极，并且其中该第二半导体器件能够位于安装衬底的孔部分中，并且其中第一半导体 器件能够通过引线端子支撑在安装基板上; 并且两个半导体器件的凸块电极彼此电连接。