公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：JP2000101093A

公开(公告)日：2000-04-07

申请号：JP24211799

申请日：1999-08-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  EDWARD J NOWACK ,  WILBUR D PRISER ,  MIN H TONG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a device structure of SOI(silicon on isulator) CMOS (complementary metal oxide semiconductor) in which avalanche multiplication of current flowing through a device is increased when an FET(field effect transistor) is turned on and body charges are removed when the FET is turned off. SOLUTION: An FET having an electric floating body is substantially isolated electrically from a substrate. A high resistance path 16 for coupling the floating body is provided at the source. The resistor is operated as a floating body for active switching and a body grounded in waiting mode in order to reduce leakage current. The high resistance path has a resistance of at least 1 MΩ and made of polysilicon. The resistor is formed using a split polysilicon process for opening a hole in a first polysilicon layer in order that an embedded contact mask 19 brings a second polysilicon layer into contact with the substrate.

公开(公告)号：JPH1187712A

公开(公告)日：1999-03-30

申请号：JP19272598

申请日：1998-07-08

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FERENCE THOMAS G ,  HOOK TERENCE B ,  MARTIN DALE W

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To ensure strong resistance against hot electron effect on the interface of silicon/silicon dioxide while suppressing damage of an element by substituting deuterium for hydrogen of a film formation reactive substance being used in production of semiconductor thereby producing a deuterium film substance at the time of film formation. SOLUTION: A MOSFET element 100 comprises a single crystal silicon substrate 11, source-drain regions 12, 13, a gate oxide 14, a gate polysilicon 15, a gate sidewall spacer 16, a silicon nitride barrier wall 18, a passive oxide layer (e.g. SiO2 ) to be bonded, and a self-aligned silicate layer 17. These components of gate oxide 14, polysilicon 15, or the like, in the element contain hydrogen molecules emitted into the oxide during annealing process. The hydrogen atom is substituted by deuterium at the time of film formation to produce a deuterium film substance. Hydrogen migrates to the interface of silicon/silicon dioxide of these component of element to produce a deuterium substance thus exhibiting resistance against heat cycle.

公开(公告)号：WO2009012276A3

公开(公告)日：2009-03-26

申请号：PCT/US2008070102

申请日：2008-07-16

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

IPC: H01L21/335

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Abstract translation: 公开了不对称场效应晶体管结构（200a-c）的实施例以及形成其中源极区（204,304）（Rs）和栅极（210,310）中的两个串联电阻漏极（（ （204）和漏极区域（205）的不同高度（214,215），以便提供最佳性能（即，提供具有最小电路延迟的改进的驱动电流） 和/或源极（304）和漏极区域（305）与栅极（210,310）之间的不同距离（351,352）被调整为使源极区域（204,305）中的串联电阻最小化（即，按顺序 以确保串联电阻小于预定电阻值）并且为了同时使栅极（210,310）与漏极（205,305）的电容最小化（即，为了同时确保栅极（210,310）至 漏极（205,305）电容小于预定电容值）。

公开(公告)号：WO2005004206A3

公开(公告)日：2005-02-17

申请号：PCT/US2004021279

申请日：2004-06-30

Applicant: IBM ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

Abstract translation: 公开了一种利用互补鳍型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片（100）的第一类型FinFET以及包括平行于第一鳍片（100）延伸的第二鳍片（102）的第二类型FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域（130）与第二类型FinFET之间的绝缘体鳍状物。 绝缘体鳍状物具有与第一鳍状物（100）和第二鳍状物（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个 鳍。 本发明还具有在第一类型FinFET和第二类型FinFET的沟道区上形成的共同栅极（106）。 栅极（106）包括与第一类型FinFET相邻的第一杂质掺杂区域和与第二类型FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型的FinFET和第二类型的FinFET之间的差异有关的不同的功函数。 第一翅片（100）和第二翅片（102）具有大致相同的宽度。

公开(公告)号：DE112012000717T5

公开(公告)日：2013-11-14

申请号：DE112012000717

申请日：2012-01-18

Applicant: IBM

Inventor： SHI YUN ,  CLARK WILLIAM F

IPC: H01L21/336 ,  H01L29/78

Abstract: Es ist eine Halbleitereinheit (100) offenbart. In einer Ausführungsform beinhaltet eine Halbleitereinheit eine n-Wanne (114) innerhalb einer p-Wanne (112) in einer Siliciumschicht (107), die oben auf einer vergrabenen Oxidschicht (109) eines Silicium-auf-Isolator(SOI)-Substrats angeordnet ist; einen ersten Source-Bereich (125) und einen zweiten Source-Bereich (127) innerhalb eines Teils der p-Wanne (112); einen ersten Drain-Bereich (145) und einen zweiten Drain-Bereich (147) innerhalb eines Teils der p-Wanne (112) und innerhalb eines Teils der n-Wanne (114); sowie ein Gate (150), das oben auf der n-Wanne (114) angeordnet ist, wobei zwischen der n-Wanne (114) und der p-Wanne (112) ein Bereich mit einem lateralen hohen Feld erzeugt wird und zwischen dem Gate (150) und der n-Wanne (114) ein Bereich mit einem vertikalen hohen Feld erzeugt wird. Es ist ein zugehöriges Verfahren offenbart.

公开(公告)号：MY117189A

公开(公告)日：2004-05-31

申请号：MYPI9903633

申请日：1999-08-25

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR DAVID ,  TONG MINH H

IPC: H01L27/06 ,  H01L29/76 ,  H01L21/00 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A DEVICE DESIGN FOR AN FET IN SOL CMOS WHICH IS DESIGNED FOR ENHANCED AVALANCHE MULTIPLICATION OF CURRENT THROUGH THE DEVICE WHEN THE FET IS ON, AND TO REMOVE THE BODY CHARGE WHEN THE FET IS OFF. THE FET HAS AN ELECTRICALLY FLOATING BODY AND IS SUBSTATIALLY ELECTRICALLY ISOLATED FROM THE SUBSTRATE. THE PRESENT INVENTION PROVIDES A HIGH RESISTANCE PATH COUPLING THE FLOATING BODY OF THE FET TO THE SOURCE OF THE FET, SUCH THAT THE RESISTOR ENABLES THE DEVICE TO ACT AS A FLOATING BODY FOR ACTIVE SWITCHING PURPOSES AND AS A GROUNDED BODY IN A STANDBY MODE TO REDUCE LEAKAGE CURRENT. THE HIGH RESISTANCE PATH HAS A RESISTANCE OF AT LEAST 1 M-OHM, AND COMPRISES A POLYSILICON RESISTOR WHICH IS FABRICATED BY USING A SPLIT POLYSILICON PROCESS IN WHICH A BURIED CONTACT MASK OPENS A HOLE IN A FIRST POLYSILICON LAYER TO ALLOW A SECOND POLYSILICON LAYER TO CONTACT THE SUBSTRATE. (FIGURE 1)

公开(公告)号：AU2003223306A1

公开(公告)日：2003-10-08

申请号：AU2003223306

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

公开(公告)号：SG74635A1

公开(公告)日：2000-08-22

申请号：SG1998001415

申请日：1998-06-15

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FERENCE THOMAS G ,  HOOK TERENCE B ,  MARTIN DALE W

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/78 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336 ,  H01L21/306

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.