公开(公告)号：EP1547165A4

公开(公告)日：2009-05-27

申请号：EP03773062

申请日：2003-09-26

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  COHEN GUY MOSHE ,  MARTEL RICHARD ,  MISEWICH JAMES A ,  TSANG JAMES CHEN-HSIANG

IPC: H01L51/05 ,  H01L51/30 ,  H01L51/52 ,  H01L33/00

CPC classification number: H01L51/52 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742 ,  Y10S977/938 ,  Y10S977/949

Abstract: A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.

公开(公告)号：JP2001358156A

公开(公告)日：2001-12-26

申请号：JP2001137754

申请日：2001-05-08

Applicant: IBM

Inventor： KEVIN COCK CHAN ,  COHEN GUY MOSHE ,  RONEN ANDREW ROY ,  PAUL MICHAEL SOLOMON

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicide treating method for thin-film SOI device. SOLUTION: The self-aligned silicide-process contains a step for attaching a metal or an alloy the gate, source and drain structures formed on an SOI film a step for forming a first alloy by reacting the metal or the alloy with the SOI film at a first temperature, a step, for selectively etching the nonreactive layer of the metal (or the alloy), a step for attaching an Si film on the first alloy, a step for forming a second alloy by reacting the Si film at the second temperature and a step for selectively etching the nonreactive layer of the Si film.

公开(公告)号：WO2004030043A2

公开(公告)日：2004-04-08

申请号：PCT/US0330647

申请日：2003-09-26

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  COHEN GUY MOSHE ,  MARTEL RICHARD ,  MISEWICH JAMES A ,  TSANG JAMES CHEN-HSIANG

IPC: H01L51/05 ,  H01L51/30 ,  H01L51/52 ,  H01L

CPC classification number: H01L51/52 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742 ,  Y10S977/938 ,  Y10S977/949

Abstract: A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.

Abstract translation: 发光装置包括栅电极（101），包含用于电激发光发射的分子的通道（103），其中分子设置在栅电极（101）的有效范围内，源（104）耦合到 所述沟道的第一端将电子注入所述沟道中，以及与所述沟道的第二端连接的漏极（105）将空穴注入所述沟道中。

公开(公告)号：JP2006332662A

公开(公告)日：2006-12-07

申请号：JP2006142405

申请日：2006-05-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY MOSHE ,  SOLOMON PAUL M

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  Y10S977/762 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a vertical FET including a nanowire channel, with the access resistance to the lower contact reduced and the gate length controlled. SOLUTION: A vertical FET structure, having a nanowire which constitutes a FET channel, is disclosed. A nanowire is formed on a conductive silicide layer. The nanowire is controlled by a gate surrounding it. Upper and lower insulating plugs function as gate spacers and make the gate-source capacitance and the gate-drain capacitance reduced. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括纳米线通道的垂直FET，降低对下接触器的访问阻力，并控制栅极长度。 公开了具有构成FET沟道的纳米线的垂直FET结构。 在导电硅化物层上形成纳米线。 纳米线由周围的门控制。 上下绝缘插头用作栅极隔离层，使栅源电容和栅极 - 漏极电容减小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005072582A

公开(公告)日：2005-03-17

申请号：JP2004237676

申请日：2004-08-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY MOSHE

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a FinFET, having a strained-silicon channel (and the structure obtained). SOLUTION: A semiconductor device (and the method of manufacturing the same) includes the strained-silicon channel formed adjacent to the source and the drain, a first gate formed on the first side section of the channel, a second gate formed on the second side section of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is nonplanar. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造具有应变硅通道（以及获得的结构）的FinFET的方法。 解决方案：半导体器件（及其制造方法）包括邻近源极和漏极形成的应变硅沟道，形成在沟道的第一侧部上的第一栅极，形成在沟道的第一侧部上的第二栅极 所述沟道的第二侧部分，形成在所述第一栅极和所述应变硅沟道之间的第一栅极电介质，以及形成在所述第二栅极和所述应变硅沟道之间的第二栅极电介质。 应变硅通道是非平面的。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004200685A

公开(公告)日：2004-07-15

申请号：JP2003413962

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY MOSHE ,  OUYANG QIQING C ,  SCHAUB JEREMY DANIEL

IPC: H01L27/146 ,  H01L31/0328 ,  H01L31/08 ,  H01L31/10 ,  H01L31/103 ,  H01L31/18 ,  H04N5/335

CPC classification number: H01L31/1085 ,  H01L31/02327 ,  H01L31/035272 ,  H01L31/105

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed photodiode which essentially has very few slow carrier and substantially produces no etalon effect.
SOLUTION: This high-speed photodiode comprises a photodetector 110, a substrate 100A formed below the photodetector, and a barrier layer 105 formed on the substrate. The embedded barrier layer includes a single/double pn junction or a bubble layer to block or remove slow photon generation carriers in a region with a low drift field.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002353246A

公开(公告)日：2002-12-06

申请号：JP2002110367

申请日：2002-04-12

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

公开(公告)号：JP2003266396A

公开(公告)日：2003-09-24

申请号：JP2003006130

申请日：2003-01-14

Applicant: IBM

Inventor： COHEN GUY MOSHE ,  CORDES STEVEN ALAN ,  ROSNER JOANNA ,  TREWHELLA JEANNINE MADELYN

IPC: B81B1/00 ,  B81C1/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing micro-structures, such as micro-electromechanical structures (MEMS) or silicon optical benches. SOLUTION: The method includes using a single mask to pattern a plurality of cavity areas to be etched on a substrate in different etching steps, and then selectively choosing the cavity areas for etching. In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched on the substrate and filling at least one of the cavity areas with a distinctive filler material. The filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials 203, 205, 206, 207. The methods of the invention produce micro- structures with more accurate cavity areas by minimizing overlay error and avoiding the need for lithography over extreme topography. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002009145A

公开(公告)日：2002-01-11

申请号：JP2001136570

申请日：2001-05-07

Applicant: IBM

Inventor： COHEN GUY MOSHE ,  SADANA DEVENDRA KUMAR

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a pattern formation buried oxide film. SOLUTION: The method for forming the pattern formation buried oxide film comprises a step of carrying out implantation into a substrate, a step of forming a mask at least on part of the substrate in order to control implantation diffusion, and a step of annealing the substrate and forming a buried oxide. The mask can be selectively pattern-formed. A thinner buried oxide can be formed in a region coated by the mask than in a region exposed to an annealing atmosphere directly.

公开(公告)号：AU2003279724A8

公开(公告)日：2004-04-19

申请号：AU2003279724

申请日：2003-09-26

Applicant: IBM

Inventor： MISEWICH JAMES A ,  COHEN GUY MOSHE ,  TSANG JAMES CHEN-HSIANG ,  MARTEL RICHARD ,  AVOURIS PHAEDON

IPC: H01L51/05 ,  H01L51/30 ,  H01L51/52 ,  H01L33/00

Abstract: A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.