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    Method for forming interconnect structure
    3.
    发明专利
    Method for forming interconnect structure 有权
    形成互连结构的方法

    公开(公告)号：JP2007173795A

    公开(公告)日：2007-07-05

    申请号：JP2006319679

    申请日：2006-11-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KAUSHIK ARUM KUMAR ,  DALTON TIMOTHY JOSEPH ,  NICHOLAS COLVIN FULLER ,  STEVEN SHYNG-TSONG ,  HEIDI LEE BAKS

    IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/522

    CPC classification number: H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an interconnect structure in an organo-silicate glass based dielectric layer. SOLUTION: The method for forming a damascene interconnect structure in an organo-silicate glass layer without damaging an organo-silicate glass material comprises: a step for forming a stack of a hard mask layer over the organo-silicate glass layer; a step for defining an openings in the hard mask layer and the organo-silicate glass layer by using combination of plasma etching and a plasma photo resist removing process; and a step for executing one or a plurality of additive plasma etching processes containing no oxygen-containing species to etch the openings to the depth required for forming the damascene interconnect structure, to remove all organo-silicate materials damaged by the combination of the plasma etching and the plasma photo resist removing process. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在有机硅酸盐玻璃基电介质层中制造互连结构的方法。 解决方案：在有机硅酸盐玻璃层中形成有机硅酸盐玻璃层中的镶嵌互连结构的方法，而不损坏有机硅酸盐玻璃材料包括：在有机硅酸盐玻璃层上形成硬掩模层的堆叠的步骤; 通过等离子体蚀刻和等离子体光刻胶去除工艺的组合来限定硬掩模层和有机硅酸盐玻璃层中的开口的步骤; 以及用于执行不含含氧物质的一种或多种添加等离子体蚀刻工艺的步骤，以将开口蚀刻到形成镶嵌互连结构所需的深度，以除去由等离子体蚀刻的组合损坏的所有有机硅酸盐材料 和等离子体光刻胶去除工艺。 版权所有（C）2007，JPO＆INPIT

    Method for forming a porous dielectric material layer in a semiconductor device and device formed
    7.
    发明专利
    Method for forming a porous dielectric material layer in a semiconductor device and device formed 未知

    公开(公告)号：SG125963A1

    公开(公告)日：2006-10-30

    申请号：SG200403087

    申请日：2001-12-11

    Applicant: IBM

    Inventor： DALTON TIMOTHY JOSEPH ,  GRECO STEPHEN EDWARD ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARANA V ,  PURUSHOTHAMAN SAMPATH ,  RODBELL KENNETH PARKER ,  ROSENBERG ROBERT

    IPC: H01L21/31 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

    Abstract: A method for forming a porous dielectric material layer (14) in an electronic structure (70) and the stricture (70) formed are disclosed. In the method, a porous dielectric layer (14) in a semiconductor device (70) can be formed by first forming (10) a non-porous dielectric layer (14),- then partially curing (20), patterning (30) by reactive ion etching, and final curing (40) the non-porous dielectric layer (14) at a higher temperature than the partial curing (20) temperature to transform the non-porous dielectric material (14) into a porous dielectric material (14), thus achieving 'a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material (14) may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

    Multiple layer resist scheme implementing etch recipe particular to each layer
    8.
    发明专利
    Multiple layer resist scheme implementing etch recipe particular to each layer 未知

    公开(公告)号：SG122018A1

    公开(公告)日：2006-05-26

    申请号：SG200506915

    申请日：2005-10-31

    Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

    Inventor： FULLER NICHOLAS C M ,  DALTON TIMOTHY JOSEPH ,  JOY RAYMOND ,  LIN YI-HSIUNG ,  LOW CHUN HUI

    Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

    Protective hardmask for producing interconnect structures
    9.
    发明专利
    Protective hardmask for producing interconnect structures 未知

    公开(公告)号：GB2368457A

    公开(公告)日：2002-05-01

    申请号：GB0108448

    申请日：2001-04-03

    Applicant: IBM

    Inventor： DALTON TIMOTHY JOSEPH ,  JAHNES CHRISTOPHER V ,  LIU JOYCE C ,  PURUSHOTHAMAN SAMPATH

    IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/52

    Abstract: A permanent protective hardmask 40 protects the dielectric properties of a main bulk dielectric layer 30 having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask 40 further includes a single layer 50 or dual layer 50,60 sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers 50,60 and the permanent hardmask layer 40 may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric. The protective hardmask 40 has a low dielectric constant k which may be the same or similar to that of the bulk dielectric layer 30.

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