公开(公告)号：EP1790003A4

公开(公告)日：2011-01-12

申请号：EP05784302

申请日：2005-08-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

公开(公告)号：WO2007144264A2

公开(公告)日：2007-12-21

申请号：PCT/EP2007055260

申请日：2007-05-30

Applicant: IBM ,  IBM UK ,  CAMPBELL LEVI ,  CHU RICHARD ,  ELLSWORTH MICHAEL ,  FOGEL KEITH ,  IYENGAR MADHUSUDAN ,  SCHMIDT ROGER ,  SIMONS ROBERT

Inventor： CAMPBELL LEVI ,  CHU RICHARD ,  ELLSWORTH MICHAEL ,  FOGEL KEITH ,  IYENGAR MADHUSUDAN ,  SCHMIDT ROGER ,  SIMONS ROBERT

CPC classification number: H01L23/3677 ,  H01L2224/78301 ,  Y10T29/49128 ,  Y10T29/4935 ,  H01L2924/00014

Abstract: A composite interface and methods of fabrication are provided for coupling a cooling assembly to an electronic device. The interface includes a plurality of thermally conductive wires formed of a first material having a first thermal conductivity, and a thermal interface material at least partially surrounding the wires. The interface material, which thermally interfaces the cooling assembly to a surface to be cooled of the electronic device, is a second material having a second thermal conductivity, wherein the first thermal conductivity is greater than the second thermal conductivity. At least some wires reside partially over a first region of higher heat flux and extend partially over a second region of lower heat flux, wherein the first and second regions are different regions of the surface to be cooled. These wires function as thermal spreaders facilitating heat transfer from the surface to be cooled to the cooling assembly.

Abstract translation: 提供了复合界面和制造方法，用于将冷却组件连接到电子设备。 界面包括由具有第一导热性的第一材料形成的多个导热丝，以及至少部分地围绕线的热界面材料。 将冷却组件与待冷却的电子设备的表面热接合的界面材料是具有第二导热性的第二材料，其中第一热导率大于第二导热系数。 至少一些线部分地位于较高热通量的第一区域上，并部分地延伸在较低热通量的第二区域上，其中第一和第二区域是待冷却表面的不同区域。 这些电线作为热扩散器起促进从待冷却表面到冷却组件的热传递。

公开(公告)号：JP2006100479A

公开(公告)日：2006-04-13

申请号：JP2004283273

申请日：2004-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHOE KWANG SU ,  FOGEL KEITH ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/265

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator (SOI) substrate structure and a manufacturing method thereof which are simple and cost-efficient.
SOLUTION: The method for manufacturing the SOI substrate structure is provided by oxidizing porous Si having a gradient. This porous Si having the gradient is formed by first implanting a (p-type or n-type) dopant into a substrate containing Si, activating this dopant using an activating annealing step, and then anodizing this implanted and activated dopant region in a solution containing HF. This Si having the gradient has a relatively coarse upper surface layer and a fine porous layer buried directly under this upper surface layer. According to the oxidation step, the fine buried porous layer is changed into a buried oxide layer, and the coarse upper surface layer is fused into a solid Si containing over-layer due to surface migration of Si atoms.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种简单且成本有效的绝缘体上硅（SOI）衬底结构及其制造方法。 解决方案：通过氧化具有梯度的多孔Si来提供SOI衬底结构的制造方法。 具有梯度的该多孔Si通过首先将（p型或n型）掺杂剂注入到含有Si的衬底中，使用活化退火步骤激活该掺杂剂，然后将该注入和活化的掺杂剂区域阳极氧化在含有 HF。 具有梯度的Si具有相对粗糙的上表面层和直接埋在该上表面层下方的细多孔层。 根据氧化步骤，由于Si原子的表面迁移，精细埋入多孔层变成掩埋氧化物层，粗糙的上表面层被熔融成为含有Si的固体Si层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2006017640B1

公开(公告)日：2006-04-27

申请号：PCT/US2005027691

申请日：2005-08-04

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

Abstract translation: 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41） 在第二沉积步骤中将另一元素的第二层（42）沉积在第一层上; 并重复第一沉积步骤和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自厚度符合组合SiGe层的所需组成比。 组合的SiGe层（50）的特征在于Si和Ge的数字合金，其导热率大于Si和Ge的无规合金的导热率。 该方法可以进一步包括在组合的SiGe层（50）上沉积Si层（61）的步骤; 组合的SiGe层的特征在于弛豫SiGe层，并且Si层（61）是应变Si层。 为了在SiGe层中具有更大的导热性，可以沉积第一层和第二层，使得每个层基本上由单一的同位素组成。

公开(公告)号：GB2494014A

公开(公告)日：2013-02-27

申请号：GB201209766

申请日：2012-06-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  LIU XIAO HU ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A spalling method includes depositing a stressor layer (5) on surface of a base substrate, and contacting the stressor layer with a planar transfer surface (15). The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate (10). The cleaved film (11) peels away from the base substrate and transfers to the planar transfer surface. The fixed distance of the vertical offset provides a uniform spalling force. Rather than using a planar transfer surface a transfer roller (30) can also be used. The roller has a curvature which is equal to the equilibrium curvature of the spalled material. There may also be an adhesive layer between the stressor layer and base substrate. The base substrate may be a semiconductor.

公开(公告)号：GB2494014B

公开(公告)日：2013-07-17

申请号：GB201209766

申请日：2012-06-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  LIU XIAO HU ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

公开(公告)号：DE112011100105T5

公开(公告)日：2012-10-31

申请号：DE112011100105

申请日：2011-02-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH ,  LAURO PAUL A ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L21/304 ,  B28D5/00

Abstract: Ein Verfahren zum Abspalten einer Schicht von einem Block eines Halbleitersubstrats beinhaltet Ausbilden einer Metallschicht auf dem Block des Halbleitersubstrats, wobei eine Zugspannung in der Metallschicht so eingerichtet ist, dass ein Bruch in dem Block verursacht wird; und Entfernen der Schicht von dem Block an dem Bruch. Ein System zum Abspalten einer Schicht von einem Block eines Halbleitersubstrats beinhaltet eine Metallschicht, die auf dem Block des Halbleitersubstrats ausgebildet ist, wobei eine Zugspannung in der Metallschicht so eingerichtet ist, dass ein Bruch in dem Block verursacht wird, und wobei die Schicht so eingerichtet ist, dass sie an dem Bruch von dem Block entfernt wird.

公开(公告)号：GB2492444B

公开(公告)日：2013-08-14

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18

公开(公告)号：DE112011100445T5

公开(公告)日：2013-04-04

申请号：DE112011100445

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES ,  KIM JEE HWAN ,  INNS DANIEL

IPC: H01L21/18

Abstract: Ein Verfahren für den Schichttransfer unter Verwendung einer mit Bor dotierten Silicium-Germanium(SiGe)-Schicht beinhaltet das Bilden einer mit Bor dotierten SiGe-Schicht auf einem Volumen-Silicium-Substrat; das Bilden einer oberen Silicium(Si)-Schicht über der mit Bor dotierten SiGe-Schicht; das Wasserstoffpassivieren der mit Bor dotierten SiGe-Schicht; das Verbinden der oberen Si-Schicht mit einem alternativen Substrat; und das Fortpflanzen einer Bruchstelle an einer Grenzfläche zwischen der mit Bor dotierten SiGe-Schicht und dem Volumen-Silicium-Substrat. Ein System für den Schichttransfer unter Verwendung einer mit Bor dotierten Silicium-Germanium(SiGe)-Schicht beinhaltet ein Volumen-Silicium-Substrat; eine auf dem Volumen-Silicium-Substrat gebildete, mit Bor dotierte SiGe-Schicht, so dass sich die mit Bor dotierte SiGe-Schicht unter einer oberen Silicium(Si)-Schicht befindet, wobei die mit Bor dotierte SiGe-Schicht so ausgebildet ist, dass sich nach Wasserstoffpassivieren der mit Bor dotierten SiGe-Schicht eine Bruchstelle an einer Grenzfläche zwischen der mit Bor dotierten SiGe-Schicht und dem Volumen-Silicium-Substrat fortpflanzt; und ein alternatives, mit der oberen Si-Schicht verbundenes Substrat.

公开(公告)号：AT368939T

公开(公告)日：2007-08-15

申请号：AT04809708

申请日：2004-09-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  CHOE KWANG SU ,  FOGEL KEITH ,  SADANA DEVENDRA

IPC: H01L21/762 ,  C22F1/10 ,  H01L21/20

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.