Method of forming a microwave array transistor for low-noise and high-power applications
    1.
    发明授权
    Method of forming a microwave array transistor for low-noise and high-power applications 失效
    形成用于低噪声和大功率应用的微波阵列晶体管的方法

    公开(公告)号:US6423603B2

    公开(公告)日:2002-07-23

    申请号:US92165601

    申请日:2001-08-06

    Applicant: IBM

    CPC classification number: H01L29/73 H01L27/0823 H01L29/0692

    Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

    Abstract translation: 一种包括多个晶体管的晶体管阵列。 每个晶体管包括发射极。 发射极区域接触覆盖每个发射极区域。 至少一个基极区域位于每个发射极区域的下面,并且对阵列中的多个晶体管是共同的。 至少一个基极接触覆盖至少一个基极区域并与每个晶体管相关联。 多个基极触点对于阵列中的至少两个晶体管是共同的。 至少一个集电极通过与每个晶体管相关联。 通过接触覆盖的收集器覆盖每个收集器到达。 导电材料的埋层子集电极区域将集电极到达区域电连接到每个晶体管的集电极基座区域。

    INTEGRATED TOROIDAL COIL INDUCTORS FOR IC DEVICES
    2.
    发明公开
    INTEGRATED TOROIDAL COIL INDUCTORS FOR IC DEVICES 有权
    INTEGRIERTETOROIDSPULENINDUKTIVITÄTENFÜRIC-BAUELEMENTE

    公开(公告)号:EP1374314A4

    公开(公告)日:2008-03-12

    申请号:EP02725187

    申请日:2002-03-13

    Applicant: IBM

    Abstract: A means for fabrication of solenoidal inductors interated in a semiconductor chip is provided. A solenoidal coil (50) is partially embedded in a deep well etched into the chip substrate (10). The non-embedded part (30) of the coil is fabricated as part of BEOL metallization layers (52). This allows for large cross-sectional area of the solenoid turns, tus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The farbication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric (14) followed by fabrication of the part of the coil (22) that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric (24 and 28) and planarization of the same by CMP. After planarization the fabrication of the remaining part (30) of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil, part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    Abstract translation: 提供了用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈(50)部分地嵌入深蚀刻到芯片衬底(10)中的深井中。 线圈的非嵌入部分(30)被制造为BEOL金属化层(52)的一部分。 这允许电磁线圈的大横截面积,从而减小了匝间电容耦合。 由于本发明的螺线管线圈具有大直径横截面,因此线圈可以制成具有大电感值并且占用芯片的小面积。 在所有FEOL步骤完成之后,远程处理包括蚀刻衬底中的深腔; 用电介质(14)为所述空腔加衬里,随后制造将通过掩模沉积导电材料金属而嵌入的线圈(22)部分; 电介质(24和28)的沉积以及通过CMP对其进行平坦化。 在平面化之后,螺线管线圈的剩余部分(30)的制造被制造为BEOL中的金属化的一部分(即,BEOL的线路/通孔)。 为了进一步增加螺线管线圈的横截面,可以通过BEOL层上面的掩模通过电沉积来建立其一部分。

    MICRO-ELECTROMECHANICAL VARACTOR WITH ENHANCED TUNING RANGE
    3.
    发明申请
    MICRO-ELECTROMECHANICAL VARACTOR WITH ENHANCED TUNING RANGE 审中-公开
    具有增强调谐范围的微电子变压器

    公开(公告)号:WO2004038916A3

    公开(公告)日:2004-08-12

    申请号:PCT/EP0312399

    申请日:2003-09-18

    Applicant: IBM IBM FRANCE

    CPC classification number: H01G5/18 B81B2201/01 H01G5/011 Y10S257/924

    Abstract: A three-dimensional micro-electromechanical (MEM) varactor is described wherein a movable beam (50) and fixed electrodes (51) are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

    Abstract translation: 描述了三维微机电(MEM)变容二极管,其中可移动光束(50)和固定电极(51)分别制造在彼此耦合的分离的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造,而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时,芯片侧器件被切割并“翻转”,对准并接合到“载体”衬底以形成最终器件。 梳状驱动(鳍)电极用于致动,同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定,可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时,可以使用较低的致动电压。 在制造时,MEMS器件被完全封装,不需要额外的器件封装。 此外,由于可以在晶片规模(晶片级MEMS封装)上进行取向和接合,所以可以以更低的成本获得改进的器件产量。

    METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES
    7.
    发明公开
    METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES 有权
    用于生产机电MICRO SWITCH CMOS兼容SUBSTRATES

    公开(公告)号:EP1461828A4

    公开(公告)日:2005-09-28

    申请号:EP02803310

    申请日:2002-11-07

    Applicant: IBM

    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

    INTEGRATED VARIABLE INDUCTOR, INDUCTOR/VARACTOR TUNING CIRCUIT

    公开(公告)号:JP2002280222A

    公开(公告)日:2002-09-27

    申请号:JP2002060436

    申请日:2002-03-06

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a novel improved integrated variable inductor and an inductor/varactor tuning circuit. SOLUTION: The magnetic field of the inductor 32 is reduced by the presence of one or more single-loop winding 34 disposed near the inductor. The single- loop winding has an open circuit, which is selectively closed, and the single loop winding is magnetically coupled to the inductor. The varactor 30 is connected to the inductor to form the inductor/varactor tuning circuit.

    INTEGRATED TOROIDAL COIL INDUCTORS FOR IC DEVICES
    10.
    发明申请
    INTEGRATED TOROIDAL COIL INDUCTORS FOR IC DEVICES 审中-公开
    集成器件的集成式电感线圈电感器

    公开(公告)号:WO02073702A9

    公开(公告)日:2003-03-20

    申请号:PCT/US0207992

    申请日:2002-03-13

    Applicant: IBM

    Abstract: A means for fabrication of solenoidal inductors interated in a semiconductor chip is provided. A solenoidal coil (50) is partially embedded in a deep well etched into the chip substrate (10). The non-embedded part (30) of the coil is fabricated as part of BEOL metallization layers (52). This allows for large cross-sectional area of the solenoid turns, tus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The farbication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric (14) followed by fabrication of the part of the coil (22) that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric (24 and 28) and planarization of the same by CMP. After planarization the fabrication of the remaining part (30) of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil, part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    Abstract translation: 提供了一种用于制造交错在半导体芯片中的螺线管电感器的装置。 螺线管线圈(50)被部分地嵌入到蚀刻到芯片衬底(10)中的深阱中。 线圈的非嵌入部分(30)被制造为BEOL金属化层(52)的一部分。 这允许螺线管转弯的大截面积,减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面,所以线圈可以制造成具有大的电感值,并且占据芯片的小面积。 改进方法包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质(14)衬里所述空腔,随后制造将通过掩模沉积导电材料金属而嵌入的线圈(22)的部分; 介电(24和28)的沉积和CMP的平坦化。 在平坦化之后,螺线管线圈的剩余部分(30)的制造被制造为BEOL中的金属化的一部分(即,作为BEOL的线/通路)。 为了进一步增加螺线管线圈的横截面,其一部分可以通过电沉积穿过BEOL层顶部的掩模来构建。

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