公开(公告)号：EP2011208A4

公开(公告)日：2011-09-28

申请号：EP07759794

申请日：2007-03-30

Applicant: IBM

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：JP2012054555A

公开(公告)日：2012-03-15

申请号：JP2011187435

申请日：2011-08-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICKY S AMOS ,  BOYD DIANE C ,  CYRIL CABRAL JR ,  RICHARD D KAPLAN ,  JAKUB T KEDZIERSKI ,  VICTOR KU ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  ANNE L ZEUGEN ,  SERENDRA MAHESWARAN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.

Abstract translation: 要解决的问题：提供允许在栅极电介质上制备多个硅化物金属栅极的互补金属氧化物半导体集成工艺。 解决方案：提供了一种CMOS硅化物金属栅极集成方法，其能够消除改变硅化物金属栅极相的多晶硅栅极原料的高度变化的缺点。 该集成方法最小化了工艺的复杂性，从而抑制了CMOS晶体管的制造成本增加。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：WO2005083780A2

公开(公告)日：2005-09-09

申请号：PCT/US2005005565

申请日：2005-02-22

Applicant: IBM ,  AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

Inventor： AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract translation: 本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。 不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。 本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：WO2007115146A3

公开(公告)日：2008-04-24

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。

公开(公告)号：WO2007115146B1

公开(公告)日：2008-06-05

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

公开(公告)号：JP2007300103A

公开(公告)日：2007-11-15

申请号：JP2007113990

申请日：2007-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MOCUTA ANDA C ,  CHIDAMBARRAO DURESETI ,  DONATON RICARDO A ,  KERN RIM ,  ONSONGO DAVID MASARA

IPC: H01L21/20 ,  H01L21/338 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To reduce the formation of misfit dislocation that may reduce the charge mobility and device performance. SOLUTION: There is provided a method of manufacturing a semiconductor structure and a semiconductor device, more specifically, an N-type FET device. The device includes a stress receiving layer provided on a stress inducing layer via a material at an interface between the layers, which reduces the occurrence and propagation of misfit dislocation in the structure. The stress receiving layer includes silicon (Si), the stress inducing layer includes silicon-germanium (SiGe), and the material includes carbon given by doping both layers during the period of the formation of the device. The carbon can be doped over the entire SiGe layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：减少可能降低电荷迁移率和器件性能的失配位错的形成。 解决方案：提供一种制造半导体结构和半导体器件的方法，更具体地说，涉及一种N型FET器件。 该装置包括通过层之间的界面处的材料在应力诱导层上提供的应力接收层，这减少了结构中失配位错的发生和传播。 应力接收层包括硅（Si），应力诱导层包括硅锗（SiGe），并且该材料包括在器件形成期间通过掺杂两层给出的碳。 碳可以掺杂在整个SiGe层上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003332462A

公开(公告)日：2003-11-21

申请号：JP2003109064

申请日：2003-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MOCUTA ANDA C ,  IEONG MEIKEI ,  AMOS RICKY S ,  DAINE C BOYD ,  MOCUTA DAN M ,  CHEN HUAJIE

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: PROBLEM TO BE SOLVED: To provide a high performance (surface channel) CMOS device provided with a mid gap work function metal gate.
SOLUTION: An epitaxial layer is used for adjustment/reduction of a threshold voltage V
t of PFET region and large amount of reduction in V
t (up to 500 mV) which are required by a CMOS device provided with a mid gap metal gate. In this case, the counter doping using an in-site B (boron) doped epitaxial layer or B and C (carbon) codoped epitaxial layer is provided. Here, the doping of C is important to give a surface channel CMOS device provided with the mid gap metal gate while an excellent short channel effect is maintained by holding the shallow B profile through the additional degree of freedom to relaxing the diffusion of B (even in the case of the subsequent activation heat cycle).
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种具有中间间隙功能金属栅极的高性能（表面通道）CMOS器件。 解决方案：使用外延层来调整/降低PFET区域的阈值电压V t ，并且V T 的大量还原（高达500mV ），这是由设置有中间间隙金属栅极的CMOS器件所需要的。 在这种情况下，提供使用现场B（硼）掺杂外延层或B和C（碳）共掺杂外延层的反掺杂。 这里，C的掺杂对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是重要的，同时通过保持浅的B分布通过附加的自由度来放宽B的扩散（甚至 在随后的活化热循环的情况下）。 版权所有（C）2004，JPO

公开(公告)号：JP2002324903A

公开(公告)日：2002-11-08

申请号：JP2002068920

申请日：2002-03-13

Applicant: IBM

Inventor： KHARE MUKESH ,  AGNELLO PAUL D ,  CHOU ANTHONY I ,  HOOK TERENCE B ,  MOCUTA ANDA C

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and circuit configuration effective for reducing plasma-induced charging damage on a device fabricated on a silicon-on- insulator(SOI) substrate. SOLUTION: An SOI circuit configuration effective for minimizing plasma- induced charging damage during fabrication comprises formation of charge collectors connected to the gate electrode and a semiconductor body, wherein each of the charge collectors has the same or substantially the same shape and dimension. The formation of a connecting structure between a device formed on the SOI substrate and the substrate is delayed until the later stages of processing.

公开(公告)号：SG173260A1

公开(公告)日：2011-08-29

申请号：SG2010096741

申请日：2010-12-29

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  FREESCALE SEMICONDUCTOR INC ,  INFINEON TECHNOLOGIES CORP ,  FRANCK ARNAUD

Inventor： XIANGDONG CHEN ,  WEIPENG LI ,  MOCUTA ANDA C ,  DAE-GYU PARK ,  SHERONY MELANIE J ,  STEIN KENNETH J ,  HAIZHOU YIN ,  JIN-PING HAN ,  LAEGU KANG ,  MENG LEE YONG ,  WAY TEH YOUNG ,  VOON-YEW THEAN ,  DA ZHANG ,  ARNAUD FRANCK

Abstract: OF THE DISCLOSUREBALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERSAn integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Fig. 3