公开(公告)号：JP2001358156A

公开(公告)日：2001-12-26

申请号：JP2001137754

申请日：2001-05-08

Applicant: IBM

Inventor： KEVIN COCK CHAN ,  COHEN GUY MOSHE ,  RONEN ANDREW ROY ,  PAUL MICHAEL SOLOMON

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicide treating method for thin-film SOI device. SOLUTION: The self-aligned silicide-process contains a step for attaching a metal or an alloy the gate, source and drain structures formed on an SOI film a step for forming a first alloy by reacting the metal or the alloy with the SOI film at a first temperature, a step, for selectively etching the nonreactive layer of the metal (or the alloy), a step for attaching an Si film on the first alloy, a step for forming a second alloy by reacting the Si film at the second temperature and a step for selectively etching the nonreactive layer of the Si film.

公开(公告)号：JP2002141504A

公开(公告)日：2002-05-17

申请号：JP2001209862

申请日：2001-07-10

Applicant: IBM

Inventor： LEE KAM-LEUNG ,  RONEN ANDREW ROY

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a CMOS device that substantially eliminates increased transient speed diffusion in a dopant, and has an extremely shallow junction. SOLUTION: In the COMS device, the dopant is injected to a substrate 10 containing Si, a dope region 12 is formed, a metal layer 14 is formed on the substrate containing Si, the metal layer is heated to change into a metal silicide layer 16, the dope region is simultaneously activated, a vacancy formed by heating is joined to an interstitial atom formed by the process, and the transient diffusion in the dopant on the substrate containing Si is substantially eliminated.

公开(公告)号：JP2002151690A

公开(公告)日：2002-05-24

申请号：JP2001286248

申请日：2001-09-20

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  RONEN ANDREW ROY

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a sub 0.1 μm MOSFET device wherein depletion of polysilicon is minimum, a source junction and a drain junction of silicide are comprised, and a sheet resistance of a poly gate is very low. SOLUTION: A damascen gate process is used wherein, with a dummy gate region provided, the injection/activation annealing and siliciding of a source and drain are performed, and then the dummy gate region is removed and replaced with a polysilicon gate region. Thus, a high-performance sub 0.1 μm MOSFET device is provided in which the sheet resistance of the poly gate is 5 Ω/(square) or below.

公开(公告)号：JPH1154454A

公开(公告)日：1999-02-26

申请号：JP19988497

申请日：1997-07-25

Applicant: IBM

Inventor： CABRAL JR CYRIL ,  LAWRENCE ALFRED CLEVENGER ,  FRANCOIS MAXDOLE ,  HARPER JAMES M E ,  MANN RANDY W ,  GLENN LESTER MILES ,  NAKOS JAMES S ,  RONEN ANDREW ROY ,  CATHERINE L SAENGER

IPC: C22C14/00 ,  C30B3/00 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a C54 phase titanium silicide without requiring a second high-temperature annealing. SOLUTION: A low resistivity titanium silicide and semiconductor devices incorporating the same are formed by a titanium alloy comprising titanium and 1-20 atom percent refractory metal deposited in a layer overlying a silicon substrate. The substrate is then heated to a temperature which is sufficient to practically form a C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, but more preferably be Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 deg.C, and more preferably between about 600 to 700 deg.C.