FORMATION METHOD OF EXTREMELY SHALLOW JUNCTION

    公开(公告)号:JP2002141504A

    公开(公告)日:2002-05-17

    申请号:JP2001209862

    申请日:2001-07-10

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a CMOS device that substantially eliminates increased transient speed diffusion in a dopant, and has an extremely shallow junction. SOLUTION: In the COMS device, the dopant is injected to a substrate 10 containing Si, a dope region 12 is formed, a metal layer 14 is formed on the substrate containing Si, the metal layer is heated to change into a metal silicide layer 16, the dope region is simultaneously activated, a vacancy formed by heating is joined to an interstitial atom formed by the process, and the transient diffusion in the dopant on the substrate containing Si is substantially eliminated.

    MANUFACTURING METHOD OF MOSFET DEVICE
    3.
    发明专利

    公开(公告)号:JP2002151690A

    公开(公告)日:2002-05-24

    申请号:JP2001286248

    申请日:2001-09-20

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a sub 0.1 μm MOSFET device wherein depletion of polysilicon is minimum, a source junction and a drain junction of silicide are comprised, and a sheet resistance of a poly gate is very low. SOLUTION: A damascen gate process is used wherein, with a dummy gate region provided, the injection/activation annealing and siliciding of a source and drain are performed, and then the dummy gate region is removed and replaced with a polysilicon gate region. Thus, a high-performance sub 0.1 μm MOSFET device is provided in which the sheet resistance of the poly gate is 5 Ω/(square) or below.

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