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    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS
    2.
    发明公开
    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS 审中-公开
    连接结构与改进的电性能迁移集成电路的

    公开(公告)号：EP2283515A4

    公开(公告)日：2014-10-22

    申请号：EP09759016

    申请日：2009-05-22

    Applicant: IBM

    Inventor： FILIPPI RONALD ,  CHANDRA KAUSHIK ,  SANKARAN SUJATHA ,  HU CHAO-KUN ,  STANDAERT THEODORUS ,  GRUNOW STEPHAN ,  SIMON ANDREW H

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

    COPPER INTERCONNECTION OF METAL SEED LAYER INSERTION STRUCTURE
    3.
    发明专利
    COPPER INTERCONNECTION OF METAL SEED LAYER INSERTION STRUCTURE 失效

    公开(公告)号：JPH11340229A

    公开(公告)日：1999-12-10

    申请号：JP11751399

    申请日：1999-04-26

    Applicant: IBM

    Inventor： EDELSTEIN DANIEL CHARLES ,  HARPER JAMES MCKELL EDWIN ,  HU CHAO-KUN ,  SIMON ANDREW H ,  UZOH CYPRIAN EMEKA

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnected structure of copper alloys having improved electromigration resistance force, adhesion and other surface characteristics. SOLUTION: Copper conductor bodies 56 and 60 and a copper alloy or metal seed layer 76 disposed between the copper conductor bodies and an electronic device are utilized to provide a novel interconnected structure for establishing electrical communication with the electronic device. In order to improve the electromigration resistance force, an adhesion property to a barrier layer, device surface characteristics or an adhesion process, copper-based seed layers of various decompositions or a specific metal seed layer can be used according to each purpose.

    STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL
    4.
    发明申请
    STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL 审中-公开
    结构和方法替代金属门和接触金属

    公开(公告)号：WO2011109203A2

    公开(公告)日：2011-09-09

    申请号：PCT/US2011025976

    申请日：2011-02-24

    Applicant: IBM ,  SIMON ANDREW H ,  KWON UNOH ,  LI ZHENGWEN ,  WONG KEITH KWONG HON ,  PAPADATOS FILIPPOS ,  CHUDZIK MICHAEL P

    Inventor： SIMON ANDREW H ,  KWON UNOH ,  LI ZHENGWEN ,  WONG KEITH KWONG HON ,  PAPADATOS FILIPPOS ,  CHUDZIK MICHAEL P

    CPC classification number: H01L23/485 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrical device is provided with a p-type semiconductor device (105) having a first gate structure (60) that includes a gate dielectric (10) on top of a semiconductor substrate (5), a p-type work function metal layer (25), a metal layer (28) composed of titanium and aluminum, and a metal fill (29 ) composed of aluminum. An n-type semiconductor device (100) is also present, on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric (30) is present over the semiconductor substrate. The interlevel dielectric includes interconnects (80) to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminium, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

    Abstract translation: 电气装置设置有具有第一栅极结构（60）的p型半导体器件（105），第一栅极结构（60）包括在半导体衬底（5）的顶部上的栅极电介质（10），p型功函数金属层 25），由钛和铝构成的金属层（28）和由铝构成的金属填充物（29）。 在半导体衬底上还存在n型半导体器件（100），该半导体衬底包括包括栅极电介质的第二栅极结构，由钛和铝构成的金属层和由铝构成的金属填充物。 层间电介质（30）存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连（80）。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。

    INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY
    6.
    发明申请
    INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY 审中-公开
    具有增强可靠性的互连结构

    公开(公告)号：WO2012058011A3

    公开(公告)日：2012-06-14

    申请号：PCT/US2011056119

    申请日：2011-10-13

    Applicant: IBM ,  FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

    Inventor： FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

    IPC: H01L21/28 ,  H01L21/768

    CPC classification number: H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved interconnect structure including a dielectric layer (202) having a conductive feature (204) embedded therein, the conductive feature (204) having a first top surface (208) that is substantially coplanar with a second top surface (206) of the dielectric layer (202); a metal cap layer (212) located directly on the first top surface (208), wherein the metal cap layer (212) does not substantially extend onto the second top surface (206); a first dielectric cap layer (21 0A) located directly on the second top surface (206), wherein the first dielectric cap layer (21 0A) does not substantially extend onto the first top surface (208) and the first dielectric cap layer (210A) is thicker than the metal cap layer (212); and a second dielectric cap layer (220) on the metal cap layer (212) and the first dielectric cap layer (210A). A method of forming the interconnect structure is also provided.

    Abstract translation: 一种改进的互连结构，包括具有嵌入其中的导电部件（204）的电介质层（202），所述导电部件（204）具有与电介质的第二顶表面（206）基本共面的第一顶表面 层（202）; 直接位于所述第一顶面（208）上的金属盖层（212），其中所述金属盖层（212）基本上不延伸到所述第二顶面（206）上; 直接位于第二顶表面（206）上的第一电介质盖层（210A），其中第一电介质盖层（210A）基本上不延伸到第一顶表面（208）上并且第一电介质盖层（210A） ）比金属盖层（212）厚; 和在金属盖层（212）和第一电介质盖层（210A）上的第二电介质盖层（220）。 还提供了形成互连结构的方法。

    MICROSTRUCTURE HAVING ELECTROMIGRATION RESISTANCE AND MANUFACTURE THEREOF
    9.
    发明专利
    MICROSTRUCTURE HAVING ELECTROMIGRATION RESISTANCE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2000174025A

    公开(公告)日：2000-06-23

    申请号：JP29247099

    申请日：1999-10-14

    Applicant: IBM

    Inventor： SAIPUREIN E UZOO ,  STEPHEN H BETCHER ,  PATRICK W DEHABAAN ,  PARKS CHRISTOPHER C ,  SIMON ANDREW H

    IPC: H01L21/3205 ,  C25D5/10 ,  C25D7/00 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To provide a high concn. impurity content and a resistance to the crystal grain growth by keeping a substrate in a plating soln. after electrodepositing a Cu-contg. film on a seed layer of the substrate dipped in the plating soln., electrodepositing a Cu-contg. film, and removing and drying the substrate from the plating soln. SOLUTION: A first electrodeposited metal film layer 22 is formed on an exposed region of the top of a metal seed layer 6, an impurity film 26 is laminated on a fine structure contg. a rough surface 24' of the metal film layer 22, this film 26 has a top surface and is composed of a heavy dopant from an electroplating soln., an electrodeposited metal film layer 30 is formed on the impurity film 26. This film 26 gives a heavily doped region which is integrated with a rough surface 24' to give a nature of suppressing the crystal grain growth and the electromigration resistance to composite metal conductive wires 39. Thus it is possible to obtain a superior electric, thermodynamic and metallurgical nature.

    Graphene and metal interconnects
    10.
    发明专利
    Graphene and metal interconnects 未知

    公开(公告)号：GB2523948A

    公开(公告)日：2015-09-09

    申请号：GB201511991

    申请日：2013-12-09

    Applicant: IBM

    Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  FILIPPI RONALD G ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  CHOI SAMUEL S

    IPC: H01L23/532 ,  H01L21/768

    Abstract: A graphene and metal interconnect structure and methods of making the same. A multiple layer graphene structure may be grown using a graphene catalyst. The graphene forms an electrical connection 30 between two or more vias (16,36) or components 20, or a combination of vias and components. A via includes a fill metal, with at least a portion of the fill metal 36 being surrounded by a barrier metal 38. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300°C - 400°C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.

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