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    READ AMPLIFIER
    3.
    发明专利
    READ AMPLIFIER 失效

    公开(公告)号：JP2000286345A

    公开(公告)日：2000-10-13

    申请号：JP2000069416

    申请日：2000-03-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  LINDOLF JUERGEN ,  BORST THOMAS ,  RUCKERBAUER HERMANN

    IPC: H01L21/761 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H03F3/16

    Abstract: PROBLEM TO BE SOLVED: To adjust and set the turn-on voltage to a specified value even when using a short channel transistor in a read amplifier by installing a field-effect transistor having a variable bus tab potential in a bus tab separated from the other elements in a semiconductor substrate. SOLUTION: On an n--type semiconductor substrate 4, a p-type epitaxial layer 5 is disposed. Between the semiconductor substrate 4 and the epitaxial layer 5, an n+-type buried layer 6 is formed. The n+-type buried layer 6 forms a bus tab 9 together with an n-type drain D and n-type diffusion regions 7, 8. The diffusion regions are disposed in the bus tab 9, separating a field-effect transistor 10 having the n-type drain D, the source S, and the gate G made of polycrystalline silicon from the other elements. The bus tab potential is supplied to the field-effect transistor 10 through a p+-type region having a connection terminal B to set the turn-on voltage to a specified value.

    READING OUT METHOD FOR FUSE/ANTI-FUSE
    4.
    发明专利
    READING OUT METHOD FOR FUSE/ANTI-FUSE 失效

    公开(公告)号：JP2002056689A

    公开(公告)日：2002-02-22

    申请号：JP2001157853

    申请日：2001-05-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

    IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To prevent surely rapid deterioration process of fuse/anti-fuse and unexpected burnout of fuse/anti-fuse being never burned out hitherto in reading out fuse/anti-fuse of a semiconductor memory assembly such as especially a DRAM. SOLUTION: In reading out of fuse/anti-fuse, voltage Vb1h deciding a high potential of a bit line BL of a memory cell array 6 is used instead of internal voltage Vint being general hitherto. The voltage Vb1h is reduced for the internal voltage Vint, especially, it is preferable that voltage Vb1h is reduced by almost 20% to 30% for the internal voltage Vint.

    6.
    发明专利
    未知

    公开(公告)号：DE50100988D1

    公开(公告)日：2003-12-24

    申请号：DE50100988

    申请日：2001-06-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRASS ECKHARD ,  LE THOAI-THAI ,  LINDOLF JUERGEN ,  SCHNABEL JOACHIM

    IPC: G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C7/22 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  H03K19/0175

    Abstract: The circuit generates a control voltage derived from a reference current per differential amplifier acting as a receiver to set the correct operating point. Switching elements for each receiver in a line carrying a current for generating the control voltage are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and are closed periodically or at discrete times in standby mode by a refresh signal. The circuit generates a control voltage derived from a reference current (IREF) for each differential amplifier (6,7) functioning as a receiver to set the correct operating point. It has switching elements (10-12) for each receiver in a line (13) carrying a current for generating the control voltage and that are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and that are closed periodically or at discrete times in standby mode by a refresh signal (SRF). Independent claims are also included for the following: a DRAM memory.

    8.
    发明专利
    未知

    公开(公告)号：DE10030442B4

    公开(公告)日：2006-01-12

    申请号：DE10030442

    申请日：2000-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHR MATTHIAS ,  TEWS RENE ,  MUELLER JOCHEN ,  LINDOLF JUERGEN

    IPC: H01L21/28 ,  H01L23/525 ,  H01L23/532

    Abstract: Connecting element consists of a layer structure (1) arranged between two conducting structures. The layer structure is formed by a dielectric layer (2) which can be destroyed by applying a voltage and a silicon layer (3). The dielectric layer borders a first structure made of tungsten. Preferred Features: The dielectric layer is made of Si3N4 or SiO2. The silicon layer is made of amorphous silicon or polysilicon. The first structure made of tungsten is formed from a first conducting pathway (4) with the dielectric layer applied to its upper side.

    10.
    发明专利
    未知

    公开(公告)号：DE10139515C2

    公开(公告)日：2003-07-31

    申请号：DE10139515

    申请日：2001-08-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  LINDOLF JUERGEN

    IPC: G05F3/30 ,  H01L29/732 ,  H01L29/73 ,  H01L23/58 ,  G05F3/22

    Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

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