公开(公告)号：KR101293057B1

公开(公告)日：2013-08-05

申请号：KR1020120025574

申请日：2012-03-13

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  김대윤

IPC: H03M1/12 ,  H04N5/3745

CPC classification number: H03M1/56 ,  H03M1/0607 ,  H03M2201/23 ,  H03M2201/32 ,  H03M2201/615 ,  H03M2201/6372 ,  H04N5/3745

Abstract: PURPOSE: A comparator, an analog-to-digital (A/D) converter, a ramp signal slope compensating circuit, a complementary metal-oxide semiconductor (CMOS) image sensor containing the circuit, and a ramp signal slope compensating method in accordance with the above are provided to prevent the slope ratio of a fine ramp signal to a coarse ramp signal from being distorted due to the slope change of the fine ramp signal and to improve linearity of A/D conversion. CONSTITUTION: An A/D converter (10) includes an amplifier, a comparator (12), a first memory part (16), and a second memory part (18). The amplifier receives a pixel voltage, a reference voltage, a fine ramp voltage, and a coarse ramp voltage. The comparator is equipped with a switch, which is connected between a coarse ramp voltage input terminal receiving coarse ramp voltage input and the amplifier, and a capacitor. One end of the capacitor is connected between the switch and the amplifier, and the other end is connected to a ground voltage. The first memory part stores the most significant bit among 1 least significant bit (LSB) for the coarse ramp voltage. The second memory part stores the least significant bit among 1 LSB for the coarse ramp voltage. [Reference numerals] (12) Comparator; (14) Sink block part; (16) First memory part; (18) Second memory part; (21) Fine ramp generator; (22) Coarse ramp generator; (30) N bit counter

Abstract translation: 目的：比较器，模数（A / D）转换器，斜坡信号斜率补偿电路，含有电路的互补金属氧化物半导体（CMOS）图像传感器，以及根据 提供上述方式以防止精细斜坡信号与粗斜坡信号的斜率比由于精细斜坡信号的斜率变化而失真并提高A / D转换的线性度。 构成：A / D转换器（10）包括放大器，比较器（12），第一存储器部分（16）和第二存储器部分（18）。 放大器接收像素电压，参考电压，精细斜坡电压和粗斜坡电压。 比较器配有开关，连接在接收粗斜坡电压输入的粗斜坡电压输入端子和放大器之间，以及电容器。 电容器的一端连接在开关和放大器之间，另一端连接到接地电压。 第一个存储器部分存储粗斜坡电压的1个最低有效位（LSB）中的最高有效位。 第二存储器部分存储粗略斜坡电压的1 LSB中的最低有效位。 （附图标记）（12）比较器 （14）槽块部分; （16）第一记忆部分; （18）第二记忆部分; （21）细斜坡发生器; （22）粗斜坡发生器; （30）N位计数器

公开(公告)号：KR1020130105034A

公开(公告)日：2013-09-25

申请号：KR1020120027123

申请日：2012-03-16

Applicant: 한국과학기술원

Inventor： 조규성 ,  이대희 ,  김현덕 ,  배준형 ,  김형택 ,  김종열 ,  강동욱 ,  조민식 ,  김명수 ,  유현준

IPC: H04N5/369 ,  H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/64 ,  H03M2201/2311 ,  H03M2201/32 ,  H04N5/369

Abstract: PURPOSE: An analog to digital converter (ADC) for outputting a digitized sample signal after comparing a sample signal and a ramp signal and an image sensing apparatus applying the same are provided to increase an analog to digital (A/D) conversion speed two times faster than when exclusively using an existing up-ramp, thereby providing a high-definition image without delay. CONSTITUTION: A pixel (110) outputs an analog pixel value. A sample and hold (S/H) amplifier (120) generates a sample signal by performing a sample-and-hold operation of the analog pixel value outputted from the pixel. An ADC (130) digitizes the sample signal generated in the S/H amplifier after comparing the sample signal and multiple ramp signals. [Reference numerals] (110) Pixel; (131) Comparator-1; (132) Comparator-2; (133) Memory; (135) Compensation converter; (141) Up-lamp signal generator; (142) Down-lamp signal generator; (150) Counter

Abstract translation: 目的：提供一种用于在比较采样信号和斜坡信号之后输出数字采样信号的模/数转换器（ADC）和应用其的图像感测装置，以将模数（A / D）转换速度提高两倍 比专门使用现有的上坡更快，从而无延迟地提供高清晰度图像。 构成：像素（110）输出模拟像素值。 采样和保持（S / H）放大器（120）通过执行从像素输出的模拟像素值的采样和保持操作来产生采样信号。 在比较采样信号和多个斜坡信号之后，ADC（130）数字化S / H放大器中产生的采样信号。 （110）像素; （131）比较器-1; （132）比较器-2; （133）记忆; （135）补偿转换器; （141）上灯信号发生器; （142）筒灯信号发生器; （150）柜台

公开(公告)号：KR1020090108621A

公开(公告)日：2009-10-15

申请号：KR1020097016471

申请日：2008-04-09

Applicant: 가부시키가이샤 어드밴티스트

Inventor： 야마모토,카즈히로 ,  오카야스,토시유키

IPC: H03M1/12 ,  H03M3/02

CPC classification number: H03M3/432 ,  H03M1/12 ,  H03M3/456 ,  H03M2201/24 ,  H03M2201/32 ,  H03M2201/6135

Abstract: An AD converter converting an inputted analog signal into a digital signal is provided with an integrator outputting integrated waveforms obtained by sequentially integrating a signal level of the analog signal, a digital converting part detecting transition timing when a size relation of the signal level of the integrated waveform and a prescribed reference value transits to a prescribed state with prescribed time resolution, a feedback part controlling the signal level of the integrated waveform in accordance with a detection result in the digital converting part at a control period larger than time resolution, and a signal processing part generating the digital signal based on the detection result in the digital converting part.

Abstract translation: 将输入的模拟信号转换为数字信号的AD转换器具有：积分器，输出通过对模拟信号的信号电平进行顺序积分而得到的积分波形，数字转换部分检测转换定时， 波形和规定的参考值以规定的时间分辨率转换到规定状态，反馈部分根据大于时间分辨率的控制周期的数字转换部分中的检测结果来控制积分波形的信号电平，以及信号 处理部分基于数字转换部分中的检测结果产生数字信号。

公开(公告)号：KR1020070058395A

公开(公告)日：2007-06-08

申请号：KR1020070041228

申请日：2007-04-27

Applicant: 주식회사 애트랩

Inventor： 이방원 ,  신영호

IPC: H03M1/50 ,  H03M1/12

CPC classification number: H03M1/50 ,  H03M1/34 ,  H03M2201/32 ,  H03M2201/62

Abstract: An analog-digital converter is provided to reduce a size and power consumption by using a small number of analog elements in comparison with a conventional analog-digital converter. An analog-digital converter includes a measurement signal generator(71), a variable delay unit(72), a fixed delay unit(73), and a delay calculating and data generating unit(80). The measurement signal generator(71) generates a measurement signal(in). When the generated measurement signal(in) is changed from a low level to a high level, a switch(SW) of the variable delay unit(72) connects a ground voltage and a first capacitor(C1). The variable delay unit(72) generates a sensing signal(sen) by delaying the measurement signal(in) for a first delay. The fixed delay unit(73) generates a reference signal(ref) by delaying the measurement signal(in) for a second delay. The delay calculating and data generating unit(80) calculates a delay difference between the reference signal(ref) and the sensing signal(sen), and generates digital data having a value corresponding to the calculated delay difference.

Abstract translation: 提供了一种模拟数字转换器，用于通过使用少量的模拟元件与传统的模数转换器相比来减小尺寸和功耗。 模拟数字转换器包括测量信号发生器（71），可变延迟单元（72），固定延迟单元（73）和延迟计算和数据生成单元（80）。 测量信号发生器（71）产生测量信号（in）。 当所生成的测量信号（in）从低电平变为高电平时，可变延迟单元（72）的开关（SW）连接接地电压和第一电容器（C1）。 可变延迟单元（72）通过将测量信号（in）延迟第一延迟来产生感测信号（sen）。 固定延迟单元（73）通过将测量信号（in）延迟第二延迟来产生参考信号（ref）。 延迟计算和数据生成单元（80）计算参考信号（ref）和感测信号（sen）之间的延迟差，并产生具有与计算出的延迟差对应的值的数字数据。

公开(公告)号：KR1020140046804A

公开(公告)日：2014-04-21

申请号：KR1020120112916

申请日：2012-10-11

Applicant: 연세대학교 산학협력단

Inventor： 김여명 ,  김태욱

IPC: H03M1/50

CPC classification number: H03M1/50 ,  H03M1/34 ,  H03M2201/32 ,  H03M2201/62

Abstract: The present invention relates to a time-digital converter and a time-digital conversion method. The time-digital converter in accordance with an embodiment of the present invention includes a conversion unit converting a time difference of input signals into a voltage; a generation unit increasing a digital code and generating an analog signal corresponding to the digital code; a comparison unit comparing the voltage of the analog signal with the converted voltage; and an output unit outputting the digital code when the output signal of the comparison unit is converted.

Abstract translation: 时间数字转换器和时间 - 数字转换方法技术领域本发明涉及时间 - 数字转换器和时间 - 数字转换方法。 根据本发明的实施例的时间数字转换器包括将输入信号的时间差转换为电压的转换单元; 生成单元增加数字代码并产生对应于数字代码的模拟信号; 将模拟信号的电压与转换电压进行比较的比较单元; 以及当比较单元的输出信号被转换时输出数字代码的输出单元。

公开(公告)号：KR1020140036503A

公开(公告)日：2014-03-26

申请号：KR1020120102644

申请日：2012-09-17

Applicant: 금오공과대학교 산학협력단

Inventor： 장영찬 ,  김문규 ,  정훈주

IPC: H03M1/66

CPC classification number: H03M1/661 ,  H03M1/82 ,  H03M2201/32 ,  H03M2201/6185 ,  H03M2201/625

Abstract: The present invention relates to a technology which improves resolution by controlling the transient time to an analog level using a time-interpolation method in a digital-analog converter and suppresses the consequent increase in the area. The present invention includes a m-bit time-interpolation unit for receiving analog signals VREF(k) and VREF(k+1) supplied through (n-m)-bit reference voltage resistor column and (n-m)-bit first and second decoders, performing time-interpolation which controls the transient time from one analog level to other analog level, and outputting an analog signal (VC) having its resolution increased by m-bit. [Reference numerals] (120A) (n-m) bit decoder; (130) m-bit time-interpolation unit

Abstract translation: 本发明涉及通过使用数字 - 模拟转换器中的时间插值方法来控制模拟电平的瞬态时间来提高分辨率的技术，并且抑制了随之而来的增加的面积。 本发明包括一个m位时间插值单元，用于接收通过（nm）位参考电压电阻列和（nm）位第一和第二解码器提供的模拟信号VREF（k）和VREF（k + 1），执行 时间插值控制从一个模拟电平到其他模拟电平的瞬态时间，并输出其分辨率增加了m位的模拟信号（VC）。 （参考号）（120A）（n-m）比特解码器; （130）m位时间插值单元

公开(公告)号：KR101143247B1

公开(公告)日：2012-07-11

申请号：KR20100138361

申请日：2010-12-30

Applicant: CHEONGJU UNIVERSITY INDUSTRY & ACADEMY COOPERA TION FOUNDATION

Inventor： CHA HYEONG WOO

IPC: H03M1/12

CPC classification number: H03M1/56 ,  H03M1/002 ,  H03M1/068 ,  H03M2201/192 ,  H03M2201/2355 ,  H03M2201/32 ,  H03M2201/62

Abstract: PURPOSE: A double slope integrating ADC(Analog To Digital Converter) is provided to minimize a chip area by forming a switch control logic circuit part with a MCU(Micro Control Unit) and a single chip by using a standard CMOS(Complementary Metal Oxide Semiconductor) process. CONSTITUTION: An LOTA(Linear Operational Transconductance Amplifier) outputs a current by being applied with an analog input voltage and a reference voltage. First resistance applies the analog input voltage to an (+) input terminal in the LOTA. A first switch applies the analog input voltage to the first resistance according to a control signal. Second resistance applies the reference voltage to a (-) input terminal in the LOTA. The second switch applies the reference voltage to the second resistance according to the control signal. A capacitor outputs a voltage by charging an output current in the LOTA. A third switch initializes the output current in the LOTA and the voltage charged in the capacitor. A comparator outputs two constant voltages. A switch control logic circuit outputs the control signal controlling the operation of first, second, and third switches.

Abstract translation: 目的：提供集成ADC（模数转换器）的双斜率，通过使用标准CMOS（互补金属氧化物半导体）（MCU）与MCU（微控制单元）和单芯片形成开关控制逻辑电路部件来最小化芯片面积 ）过程。 构成：LOTA（线性运算跨导放大器）通过施加模拟输入电压和参考电压来输出电流。 第一个电阻将模拟输入电压施加到LOTA中的（+）输入端。 第一开关根据控制信号将模拟输入电压施加到第一电阻。 第二个电阻将参考电压施加到LOTA中的（ - ）输入端。 第二开关根据控制信号将参考电压施加到第二电阻。 电容器通过对LOTA中的输出电流充电来输出电压。 第三个开关初始化LOTA中的输出电流和电容中充电的电压。 比较器输出两个恒定电压。 开关控制逻辑电路输出控制第一，第二和第三开关的操作的控制信号。

公开(公告)号：KR1020090063951A

公开(公告)日：2009-06-18

申请号：KR1020070131490

申请日：2007-12-14

Applicant: 한양대학교 산학협력단

Inventor： 유창식 ,  석지환

IPC: H03M1/12

CPC classification number: H03M1/50 ,  H03M1/0607 ,  H03M1/38 ,  H03M2201/32 ,  H03M2201/6107

Abstract: An analog to digital converter using a delay locked loop and an analog to digital converting method are provided to reduce difference between the delay due to the analog input signal and the delay of the reference signal converting a digital code to analog code by using a successive approximation method and a delay locked loop. A first delay unit(10) receives a first clock signal and delays the first clock signal as much as the first delay time according to the analog input signal. A second delay unit(20) delays the first clock signal as much as the second delay time according to the reference signal converting the N bit digital signal to the analog signal. The N is a positive integer. A compensation unit(300) generates the N bit digital bit to reduce the difference between the first delay time and the second delay time and supplies the reference signal by converting the N bit digital signal to the analog signal. The compensation unit includes a delay error compensation unit and a digital to analog converter.

Abstract translation: 提供了使用延迟锁定环和模数转换方法的模数转换器，以减少由模拟输入信号引起的延迟与通过使用逐次逼近将数字码转换为模拟码的参考信号的延迟之间的差异 方法和延迟锁定环路。 第一延迟单元（10）接收第一时钟信号，并根据模拟输入信号将第一时钟信号延迟第一延迟时间。 第二延迟单元（20）根据将N位数字信号转换为模拟信号的参考信号将第一时钟信号延迟到第二延迟时间。 N是正整数。 补偿单元（300）产生N位数字位以减小第一延迟时间和第二延迟时间之间的差，并通过将N位数字信号转换为模拟信号来提供参考信号。 补偿单元包括延迟误差补偿单元和数模转换器。