公开(公告)号：AT230520T

公开(公告)日：2003-01-15

申请号：AT99308122

申请日：1999-10-14

Applicant: IBM ,  SIEMENS AG

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells (301) of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells (300) of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators (302) adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots (320) in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

公开(公告)号：MY134452A

公开(公告)日：2007-12-31

申请号：MYPI20054051

申请日：2001-05-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DIVAKARUNI RAMACHANDRA ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI-FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON-ONINSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR-LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI-FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR-LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION.HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF-REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED.(FIG 6)

公开(公告)号：DE10344862B4

公开(公告)日：2007-12-20

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE69934357T2

公开(公告)日：2007-09-20

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

公开(公告)号：AU2003202254A1

公开(公告)日：2004-08-10

申请号：AU2003202254

申请日：2003-01-08

Applicant: IBM

Inventor： WANG GENG ,  MANDELMAN JACK A ,  GAMBINO JEFFREY P

IPC: H01L21/20 ,  H01L21/308 ,  H01L21/8242

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device ( 66, 68, 70 ), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

公开(公告)号：DE69822775D1

公开(公告)日：2004-05-06

申请号：DE69822775

申请日：1998-12-23

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  MANDELMAN JACK A ,  KLEINHENZ RICHARD L

IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/407

Abstract: Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.

公开(公告)号：AU2002306174A1

公开(公告)日：2003-12-31

申请号：AU2002306174

申请日：2002-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J ,  WONG ROBERT C

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L23/535 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.

公开(公告)号：DE69904690D1

公开(公告)日：2003-02-06

申请号：DE69904690

申请日：1999-10-14

Applicant: SIEMENS AG ,  IBM

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells (301) of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells (300) of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators (302) adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots (320) in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

公开(公告)号：SG53061A1

公开(公告)日：1998-09-28

申请号：SG1997003266

申请日：1997-09-08

Applicant: IBM

Inventor： ASSADERAGHI FARIBORZ ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK A ,  SHAHIDI GHAVAM ,  VOLDMAN STEVEN H

IPC: H01L27/02 ,  H01L27/105

Abstract: A body and dual gate coupled diode for silicon-on-insulator (SOI) technology is disclosed. The body and dual gate coupled diode is formed from a SOI field-effect transistor (FET) structure. The source of the SOI FET structure forms the first terminal of the diode. The drain of the SOI FET structure forms the second terminal of the diode. The SOI FET structure includes two gates, which are tied to the body of the SOI FET structure. An SOI circuit comprising at least one body and dual gate coupled diode formed from the SOI FET structure provides electrostatic discharge (ESD) protection.