公开(公告)号：JP2001202247A

公开(公告)日：2001-07-27

申请号：JP2000356504

申请日：2000-11-22

Applicant: ST MICROELECTRONICS SRL

Inventor： OCCHIPINTI LUIGI ,  DI COLA EUSEBIO ,  LAVORGNA MARIO

IPC: G06F7/544 ,  G05B13/02 ,  G06F9/44 ,  G06F15/78 ,  G06N3/00 ,  G06N3/04 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To obtain a new neuro-fuzzy integration architecture capable of realizing on-line self-training. SOLUTION: This architecture is provided with a fuzzy type microcontroller 11 exclusive for fuzzy rule calculation and integrated on a semiconductor together with a non-volatile memory 9 so as to be monolithic, and the same IC is provided with a microprocessor 5, a volatile memory unit 2, and an arbiter block 3 connected to a bus 4 connecting the fuzzy microcontroller 11 and the microprocessor 5 and the volatile memory unit 2. The arbiter block 3 controls access to the volatile memory unit 2 by the microcontroller 5 or the fuzzy microcontroller 11. Then, an additional fuzzy co-processor 6 for fuzzy logical arithmetic processing is connected between the fuzzy microcontroller 11 and the microprocessor 5.

公开(公告)号：JP2001135100A

公开(公告)日：2001-05-18

申请号：JP2000272586

申请日：2000-09-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory device in which complete test of a word line can be performed with a low cost. SOLUTION: The non-volatile memory device integrates a memory cell array 2, a voltage generating circuit REG supplying operation voltage Vr to be adjusted to a ward line LWL1, and short circuit detecting circuit 10 in the same chip 100. The short circuit detecting circuit 10 detects output current IM1 of the voltage generating circuit REG for biasing a cell 3 of the selected word line LWL1. The output current IM1 is made a first value IM1' when short circuit is not caused, and it is made a second value IM1" when short circuit is caused between the selected word line LWL1 and adjacent word lines LWL0- LWLn. The short circuit detecting circuit 10 compares output current IM1 of the voltage generating circuit REG with the reference value Iref, and generates a short circuit digital signal Vo indicating whether short circuit is caused at an output or not.

公开(公告)号：JP2001057097A

公开(公告)日：2001-02-27

申请号：JP2000227650

申请日：2000-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10

Abstract: PROBLEM TO BE SOLVED: To obtain a single power voltage type non-volatile storage device having a hierarchical column decoder in which the bias time of a word line at the level of staircase voltage can be shortened. SOLUTION: This storage device 10 has a memory cell array 2 having structure of a form provided with global word lines 4 and local word lines 6, a global column decoding means 8 for addressing the global word lines 4, a local column decoding means 12 for addressing the local word lines 6, a global power supply means 22 for supplying power to the global column decoding means 8, and a local power supply means 24 for supplying power to a local column decoding means 12.

公开(公告)号：JP2001028197A

公开(公告)日：2001-01-30

申请号：JP2000196290

申请日：2000-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12

Abstract: PROBLEM TO BE SOLVED: To provide bias to a plurality of memory sectors in a memory element by bulk of a smaller region in a non-volatile memory element of especially a flash type and providing method for bias in a memory element. SOLUTION: A memory element 21 having a plurality of memory sectors 15 each sector of which includes a plurality of memory cells 1 is provided with a hierarchical sector decoding means. One group out of a plurality of groups of bias lines 28-32 is provided to each sector row, and is extended in parallel to a sector row. Each of a plurality of sector switching stages 35 is connected between a corresponding memory sector and a group corresponding to a bias line. A sector switching stage connected to memory sectors arranged in the same sector column is controlled by the same control signals S0, S1 supplied to a control line 40 extending in parallel to a sector column.

公开(公告)号：JP2000357396A

公开(公告)日：2000-12-26

申请号：JP2000139757

申请日：2000-05-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MANSTRETTA ALESSANDRO ,  MICHELONI RINO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory having a row redundancy function in which an access time for a memory word is drastically shortened. SOLUTION: In a non-volatile memory device having a memory cell in which rows and columns are arranged and being provided with at least one sector 100 of a matrix cell, a row decoder D and a column decoder decoding an address signal and activating rows and columns respectively, and at least one sector 110 of a redundancy cell, and being able to replace a row of a sector of a matrix cell by a row of a sector of the redundancy cell, the device is provided with a local column decoder J for a sector 100 of a matrix cell and a local column decoder L for a sector 110 of the redundancy cell. Local column decoders L for a matrix cell and for the redundancy cell are controlled by the outside signal so that rows of the sector 110 of the redundancy cell and rows of the sector 100 of a matrix cell are simultaneously activated.

公开(公告)号：JP2000244257A

公开(公告)日：2000-09-08

申请号：JP2000034045

申请日：2000-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

Abstract: PROBLEM TO BE SOLVED: To provide a digital input PWM power amplifier which is operated with high efficiency and by a comparatively low switching frequency. SOLUTION: This digital input PWM power amplifier is provided with an over-sampling noise shaping circuit, a first bus for transmitting the maximum digit bit (most significant bit) of a first number D, the second bus for transmitting the minimum digit bit (least significant bit) of the second number S and first and second PCM/PWM converters for respectively receiving the supply of first and second number bits and outputting PWM signals (MSBdig and LSBdig). The PWM signal(MSBdig) outputted by the first converter is added to the PWMsignal(LSBdig) outputted by the second one on the reverse input node(-) of an output power stage.

公开(公告)号：JP2000241515A

公开(公告)日：2000-09-08

申请号：JP2000040810

申请日：2000-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CLAUDIA CASTELLI ,  FABRIZIO FURATERUNARI ,  ADALBERTO MARIANI ,  ALEX POJEERU

IPC: H02J7/00 ,  G01R31/36 ,  H01M10/48

Abstract: PROBLEM TO BE SOLVED: To monitor the state of a battery charge by executing the trimming step of a system to substantially completely compensate for an offset. SOLUTION: A counter for determining the state of a battery charge is provided with a circuit for detecting the charge and discharged currents of a battery. An addition circuit comprises a differential amplifier AMP where an input end is connected to the terminal of a resistor Rs for detecting a battery current, and a resettable integrator stage INTEGR that integrates a signal outputted from the amplifier AMP by a switch SW. While a first comparator CompH compares a ramp that is outputted from an integrator with a first threshold VthH, and finally generates a logic charge interrupt signal INCR, a second comparator CompL compares a signal that is outputted from the integrator with a second threshold VthL, and finally generates a logic charge interrupt signal DECR.

公开(公告)号：JP2000165884A

公开(公告)日：2000-06-16

申请号：JP31914499

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： PICCINELLI EMILIANO ,  PEZZONI LUCA ,  PAU DANILO

IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

Abstract: PROBLEM TO BE SOLVED: To code video data with a more simplified hardware by calculating the complexity index of a single block at present and adding the maximum absolute difference of all blocks for fixing all the complexity indexes of a relative macro block. SOLUTION: First of all, the complexity index of a single block composing of the current macro block is calculated concerning both the styles of 'field' and 'frame'. By adding the maximum value of differences calculated to all the blocks composing of the macro block, entire macro block complexity can be provided. This calculation is repeated twice, namely, concerning the block provided when successive discrete cosine transformations(DCT) are performed in the 'frame' mode, the calculation is performed once on the line of a block corresponding to different semi-fields and the DCT is performed in the 'field' mode. Next, the second calculation is executed.

公开(公告)号：JP2000113616A

公开(公告)日：2000-04-21

申请号：JP27840799

申请日：1999-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： VIGNA BENEDETTO

IPC: G11B5/56 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  H02N1/00

Abstract: PROBLEM TO BE SOLVED: To effectively damp sedimentation vibrations (ringing) in the vicinity of read position without using a complicated closed loop control circuit by a method wherein a mechanical damping structure for restricting vibrations of a rotor element is inserted into between a part of a stator element and a part of the rotor element. SOLUTION: An integrated micro-actuator 9' connects a stator element 17' to a fixed bias region 30 where two fixed damping arms 18a", 18b" are biased at the same reference potential as a rotor element 11' via a connection part 25, and the fixed damping arms 18a", 18b" are respectively connected to fixed arms (bias regions) 20a, 20b to bias first and second drive potentials. As the results, a movable arm of the rotor element 11' arranged between the fixed damping arms 18a", 18b" is a movable damping arm 13". The fixed damping arms 18a", 18b" and the movable damping arm 13" structure as a whole a damping structure 32 for sedimentation vibrations of the rotor element 11".

公开(公告)号：JP2000112352A

公开(公告)日：2000-04-21

申请号：JP5845099

申请日：1999-03-05

Applicant: ST MICROELECTRONICS SRL

Inventor： OCCHIPINTI LUIGI ,  DI BERNARDO GIOVANNI ,  DI COLA EUSEBIO ,  CAPONETTO RICCARDO

IPC: G09C1/00 ,  H04L9/00 ,  H04L9/26 ,  H04L9/32

Abstract: PROBLEM TO BE SOLVED: To obtain a method for authentication and electronic signature of an enquiry type and a response type which have an improved security level by making a step generating a chaotic signal included in a step generating authentication and electronic signature signals. SOLUTION: A check terminal 2 checks identification data including a PIN (personal identification number) with respect to a card 1. Thereafter, the terminal 2 generates a signal or initial data X0 via a random value generating circuit 17 and moreover generates development time P. The terminal 2 transmits the initial data X0 and the signal of the development time to both of the card 1 and the chaotic generator of its own. The card 1 transfers the data and the signal to the chaotic generator 23 of its own and moreover calculates an authentication code RES' based on a secret key K' stored in a position 24 to transmit it to the terminal 2. The terminal 2 calculates a comparision code RES by using the secret key K stored in a position 29 to compare the RES with the authentication code RES' of the card 1.