公开(公告)号：KR1020050064115A

公开(公告)日：2005-06-29

申请号：KR1020030095399

申请日：2003-12-23

Applicant: 한국전자통신연구원

Inventor： 이병우 ,  박문양

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0043 ,  H03F3/45197

Abstract: 칩 사이즈 및 동작 스피드 특성을 감소시키지 않으면서 출력 전류 왜곡을 보상할 수 있는 트랜스컨덕터 회로를 개시한다. 개시된 본 발명의 트랜스컨덕터는 차동 증폭기 형태를 가지며 소정의 입력 전압이 인가되는 주 회로부, 상기 주 회로부의 몇 개의 노드와 연결되어 상기 출력 전류의 왜곡을 보상하는 보조 회로부, 출력 전류의 왜곡 보상 동작의 깊이나 정도를 제어하는 제어 전압부, 및 상기 주 회로부에 일정 바이어스를 공급하는 전류원을 포함한다.

公开(公告)号：KR1020050064114A

公开(公告)日：2005-06-29

申请号：KR1020030095398

申请日：2003-12-23

Applicant: 한국전자통신연구원

Inventor： 이병우 ,  박문양

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H03F3/45197

Abstract: 본 발명은 출력 전류의 왜곡이 보상된 트랜스컨덕터 회로를 개시한다. 개시된 본 발명의 트랜스컨덕터는 차동 증폭기 형태를 가지며, 소정의 입력 전압이 인가되는 주 회로부, 상기 주 회로부에 일정 바이어스를 공급하는 전류원, 상기 주 회로부의 몇 개의 노드와 연결되어, 상기 출력 전류의 왜곡을 보상하는 보조 회로부, 및 왜곡 보상 동작의 깊이나 정도를 제어하는 제어 전류원을 포함한다.

公开(公告)号：KR1020050048180A

公开(公告)日：2005-05-24

申请号：KR1020030082033

申请日：2003-11-19

Applicant: 한국전자통신연구원

Inventor： 이승철 ,  조민형 ,  박문양

IPC: H02M7/21

Abstract: 본 발명은 자동이득 제어기(AGC, automatic gain controller) 등에서 신호의 진폭을 검출하기 위한 회로로써 입력 신호의 AC성분의 크기에 비례하는 DC 값을 출력하는 회로이다. 제안하는 회로에서는 입력신호와 동일한 주파수를 갖는 신호를 입력신호와 혼합하여 DC 성분을 추출함으로써 빠른 동작 속도와 함께 넓은 범위의 신호 크기를 정확하게 검출할 수 있다.
제안하는 신호 진폭 검출 방법은 기본적인 신호 합성 이론에 근거하고 있다. 즉 일정 주파수를 갖는 신호를 자기 자신 혹은 자기 자신과 동일한 주파수를 갖는 구형파를 곱한 후 저대역 필터를 통과시키면 신호의 크기에 비례하는 DC 성분을 추출할 수 있다. 이러한 방법으로 기존의 다이오드를 사용한 정류기를 대치함으로써 회로의 동작속도와 신호 검출의 정확도 향상이 가능하다.

公开(公告)号：KR100466542B1

公开(公告)日：2005-01-15

申请号：KR1020020070287

申请日：2002-11-13

Applicant: 한국전자통신연구원

Inventor： 김천수 ,  박필재 ,  박문양 ,  유현규

IPC: H01L27/04

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F21/12 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Disclosed is a stacked variable inductors manufactured by stacking M (M>=2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N

Abstract translation: 本发明公开了通过堆叠中号制造的叠层可变电感器（M＆GT; = 2）在半导体衬底上的金属层，并提供叠层可变电感器，其包含1至串行连续地连接N个电感，其中每个所述电感器是在N（N＆LT形成 ; = M）彼此不同的金属层; 第一和第二端口，每个连接到所述1到N个电感器中位于最高位置的电感器和位于最低位置的电感器; 以及至少一个MOSFET，并且其中至少一个MOSFET的一个端子连接到所述第一和第二端口中的一个，并且另一个连接到在1到N个电感器之间串联连接的相邻端子中的一个。

公开(公告)号：KR100452948B1

公开(公告)日：2004-10-14

申请号：KR1020020081477

申请日：2002-12-18

Applicant: 한국전자통신연구원

Inventor： 한선호 ,  윤용식 ,  김성도 ,  박문양 ,  유현규

IPC: H03K3/027

Abstract: PURPOSE: A flipflop using complementary clocking and a prescaler using the same are provided to improve the current driving capacity by using the complementary relation between an NMOS transistor and a PMOS transistor. CONSTITUTION: A first p-type transistor(mp11) is connected between a supply voltage supply unit and the first node to receive data. A second p-type transistor(mp12) is connected between the first and the second nodes to receive the first clock. A first n-type transistor(mn11) is connected between the second node and the ground to receive the data. A third p-type transistor(mp13) is connected between the supply voltage supply unit and the third node. A second n-type transistor(mn12) is connected between the third and the fourth nodes to receive the first clock. A third n-type transistor(mn13) is connected between the fourth node and the ground. A fourth p-type transistor(mp14) is connected between the supply voltage supply unit and an output terminal. A fourth n-type transistor(mn14) is connected between the output terminal and the ground to receive the second clock. A fifth n-type transistor is connected between the first and the second nodes to receive the second clock. A fifth p-type transistor is connected between the third and the fourth nodes to receive the second clock.

Abstract translation: 目的：提供使用互补时钟的触发器和使用该触发器的预分频器，以通过使用NMOS晶体管和PMOS晶体管之间的互补关系来提高电流驱动能力。 构成：第一P型晶体管（mp11）连接在电源电压供应单元和第一节点之间以接收数据。 第二p型晶体管（mp12）连接在第一和第二节点之间以接收第一时钟。 第一n型晶体管（mn11）连接在第二节点和地之间以接收数据。 第三P型晶体管（mp13）连接在电源电压供应单元和第三节点之间。 第二n型晶体管（mn12）连接在第三和第四节点之间以接收第一时钟。 第三n型晶体管（mn13）连接在第四节点和地之间。 第四P型晶体管（mp14）连接在电源电压提供单元和输出端子之间。 第四n型晶体管（mn14）连接在输出端和地之间以接收第二时钟。 第五n型晶体管连接在第一和第二节点之间以接收第二时钟。 第五p型晶体管连接在第三和第四节点之间以接收第二时钟。

公开(公告)号：KR100441985B1

公开(公告)日：2004-07-30

申请号：KR1020010070752

申请日：2001-11-14

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  박필재 ,  김남수 ,  김천수 ,  김성도 ,  윤용식

IPC: H01P1/15

CPC classification number: H03H7/0115 ,  H03H2001/0085

Abstract: The present invention relates to an integrated filter circuit for digitally controlling characteristics of inductor and capacitor to thereby produce a controlled resonant frequency. The integrated circuit includes a number of inductors being connected in series between a high frequency input node and a high frequency output node, a plurality of capacitors each connected to a connection node of said each inductors, a plurality of switches, each connected between each capacitor and a ground and a feedback control unit for controlling the switches by sensing an output signal from the high frequency output node to thereby selectively couple each capacitor to the ground through a selected switches based on the sensed output signal.

Abstract translation: 本发明涉及一种用于数字控制电感器和电容器的特性从而产生受控谐振频率的集成滤波器电路。 集成电路包括串联连接在高频输入节点和高频输出节点之间的多个电感器，多个电容器，每个电容器连接到所述每个电感器的连接节点，多个开关，每个开关连接在每个电容器 以及接地和反馈控制单元，用于通过感测来自高频输出节点的输出信号来控制开关，从而基于感测到的输出信号通过选择的开关选择性地将每个电容器耦合到地。

公开(公告)号：KR1020040056692A

公开(公告)日：2004-07-01

申请号：KR1020020083234

申请日：2002-12-24

Applicant: 한국전자통신연구원

Inventor： 최장홍 ,  윤용식 ,  박문양

IPC: H03G3/00

Abstract: PURPOSE: A variable gain amplifier is provided to obtain characteristics such as high linearity and low noise by varying continuously gains according to input control voltages. CONSTITUTION: A variable gain amplifier includes a control signal generator, a variable resistor, and a differential amplifier. The control signal generator(210) is used for converting an external control voltage, dividing the external control voltage into a plurality of levels, and outputting the divided external control voltages as plural internal control signals. The variable resistor is used for providing variable resistance values according to the internal control signals. The differential amplifier(230) includes a parallel coupling differential amplifier having different W/L to amplify a differential element between an inverting signal and a non-inverting signal.

Abstract translation: 目的：提供可变增益放大器，以通过根据输入控制电压连续增益来获得诸如高线性度和低噪声的特性。 构成：可变增益放大器包括控制信号发生器，可变电阻器和差分放大器。 控制信号发生器（210）用于转换外部控制电压，将外部控制电压分成多个电平，并将分压的外部控制电压作为多个内部控制信号输出。 可变电阻用于根据内部控制信号提供可变电阻值。 差分放大器（230）包括具有不同W / L的并联耦合差分放大器，以放大反相信号和非反相信号之间的差分元件。

公开(公告)号：KR100424676B1

公开(公告)日：2004-03-27

申请号：KR1020010047550

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  양병도 ,  성기혁

IPC: G11C17/00

Abstract: PURPOSE: A low-power ROM is provided to be capable of reducing an area while lowering power consumption at a read operation. CONSTITUTION: Column selection transistors(Ms1-Msn) select one of a plurality of bit lines. A common connection terminal is connected in common to one ends of the column selection transistors, and precharges the bit lines with a charge sharing voltage when the column selection transistors are turned on. A precharge part(Mp1) precharges the common connection terminal with a power supply voltage(VCC). A reference voltage generating part is connected to the precharge part, and generates a reference voltage used to compare voltages of the bit lines. A sense amplifier(SA) receives the reference voltage and a charge sharing voltage of the common connection terminal.

Abstract translation: 目的：提供低功率ROM，以便在读取操作时降低功耗并减小面积。 构成：列选择晶体管（Ms1-Msn）选择多个位线中的一个。 公共连接端子共同连接到列选择晶体管的一端，并且当列选择晶体管导通时利用电荷共享电压预充电位线。 预充电部分（Mp1）利用电源电压（VCC）预充电公共连接端子。 参考电压生成部件连接到预充电部件，并且生成用于比较位线的电压的参考电压。 读出放大器（SA）接收公共连接端子的参考电压和电荷共享电压。

公开(公告)号：KR100407693B1

公开(公告)日：2003-11-28

申请号：KR1020010039998

申请日：2001-07-05

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  성기혁 ,  양병도 ,  김영준

IPC: H03B28/00

CPC classification number: G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

Abstract translation: 本发明涉及一种用于减小直接数字频率合成器（DDFS）中的ROM的尺寸的ROM分割方法，其用于在需要快速频率转换的通信系统中合成频率。 在系统中消耗大部分能量的ROM，提出了一种改进的Nicholas架构来减小ROM的尺寸。 在这种改进的Nicholas架构中，ROM分为粗略ROM和精细ROM，以将相位转换为正弦值。 本发明分别将粗略ROM和精细ROM分成量化ROM和错误ROM。 然后，存储在每个ROM中的值以一定的间隔被分段，并且每个段中的最小量化值被存储在量化ROM中，而原始ROM值和量化ROM值之间的差被存储在错误ROM中。 这样可以减少ROM的大小。 在DDFS中输入的相位值，正弦值是通过加上四个ROM值即粗量化ROM，粗误ROM，精量量ROM和微误差ROM来计算的。

公开(公告)号：KR1020030033395A

公开(公告)日：2003-05-01

申请号：KR1020010065150

申请日：2001-10-22

Applicant: 한국전자통신연구원 ,  브이케이 주식회사

Inventor： 유현규 ,  이상국 ,  박문양 ,  김성도 ,  윤용식 ,  한선호 ,  김남수 ,  오영훈

IPC: H03F1/42

Abstract: PURPOSE: A broadband high gain amplification circuit is provided to maintain a high gain and a bandwidth even though an input frequency is increased. CONSTITUTION: An amplification part(100) amplifies an input signal. An impedance control part(200) constitutes a current mirror by receiving a constant voltage(Vb1), and improves a gain of the amplification part by increasing an output impedance of the amplification part at a half power frequency where the gain of the amplification becomes a half of its peak value. The impedance control part includes an inductor(210) connected to a power supply, and a PMOS(220) having a gate connected to the constant voltage and being connected to the inductor, and a resistor(230) connected between one side of the PMOS and another side of the inductor and connected to another side of the PMOS.

Abstract translation: 目的：提供宽带高增益放大电路，以便即使输入频率增加也能保持高增益和带宽。 构成：放大部分（100）放大输入信号。 阻抗控制部分（200）通过接收恒定电压（Vb1）构成电流镜，并且通过增加放大部分的输出阻抗来提高放大部分的增益，其中放大增益变为 其峰值的一半。 阻抗控制部分包括连接到电源的电感器（210）和具有连接到恒定电压并连接到电感器的栅极的PMOS（220）和连接在PMOS的一侧之间的电阻器（230） 并且电感器的另一侧并且连接到PMOS的另一侧。