公开(公告)号：EP1211812A2

公开(公告)日：2002-06-05

申请号：EP00127649.2

申请日：2000-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

IPC: H03M1/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg).
The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB).
The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

Abstract translation: 本发明涉及到模拟 - 数字转换方法和相关的设备，在高密度的多级非易失性存储器装置。 该方法适用于多级存储器单元包括具有漏极和源极端子的浮栅晶体管; 要读出的单元是通过，施加预定的偏置电压值到它的漏极和源极端，而其漏极端子施加规定的电流值（Iref的）经受读取操作，并通过测量其栅极电压的值（Vg的 ）。 本发明的方法包括包含在所述存储器单元中的最显著位（MSB）的第一转化阶段，接着是至少显著位的第二阶段的转换（LSB）。 第一个步骤是一个时间间隙（T1-T0），其对应于栅极电压信号（VG）的上升瞬变内完成，而第二个步骤是在瞬变结束启动。

公开(公告)号：EP1178491A1

公开(公告)日：2002-02-06

申请号：EP00830553.4

申请日：2000-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Gastaldi, Roberto ,  Cappelletti, Paolo ,  Casagrande, Giulio ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory, particularly of the electrically programmable and erasable type such as a flash memory, comprises at least one two-dimensional array (SCT) of memory cells (MC) with a plurality of rows (row0-row511) and a plurality of columns (COL) of memory cells. The columns of the two-dimensional array are grouped in a plurality of packets (CP0-CP1), and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region (4) with a first type of conductivity, this region (4) being distinct from the semiconductor regions (4) with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. It is thus possible to produce memory units of very small dimensions (for example, bytes, words, or long words) which can be erased individually, without excessive overhead in terms of area.

Abstract translation: 半导体存储器，特别是诸如闪存的电可编程和可擦除类型的半导体存储器包括至少一个具有多个行（行0-行511）和多个列的存储器单元（MC）的二维阵列（SCT） （COL）的存储单元。 二维阵列的列被分组为多个分组（CP0-CP1），并且属于每个分组的列的存储器单元以第一类型的导电率形成在相应的半导体区域（4）中，这 区域（4）与半导体区域（4）不同，其中形成属于剩余包的列的存储器单元的第一导电类型。 具有第一导电类型的半导体区域将属于每行的存储器单元组划分为构成可以单独修改的基本存储器单元的多个存储器单元子集。 因此可以产生非常小尺寸的存储单元（例如，字节，单词或长单词），其可以单独擦除，而没有面积方面的过度开销。

公开(公告)号：EP1126372A1

公开(公告)日：2001-08-22

申请号：EP00830103.8

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

IPC: G06F11/20

CPC classification number: G11C29/70

Abstract: This invention relates to a non-volatile memory device (20) with configurable row redundancy, comprising:

a non-volatile memory (11) comprising of at least one matrix (11') of memory cells and at least one matrix (11") of redundant memory cells, both organised into rows and columns;
row and column decoding circuits (12,13);
read and modify circuits for reading and modifying data stored in the memory cells; and
at least one associative memory matrix (14), also organised into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix.

The memory device (20) of this invention further comprises:

at least one circuit for recognising and comparing selected row addresses (ADr) with faulty row addresses (ADrr) contained in the associative memory matrix (14), such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and
at least one configuration register (17), also comprising a matrix of non-volatile memory cells, and associated control circuits.

Abstract translation: 本发明涉及一种具有可配置行冗余性的非易失性存储器件（20），包括：非易失性存储器（11），包括至少一个存储器单元矩阵（11'）和至少一个矩阵（11“）， 冗余存储器单元，被组织成行和列;行和列解码电路（12,13）;用于读取和修改存储在存储器单元中的数据的读取和修改电路;以及至少一个关联存储器矩阵（14） 本发明的存储器件（20）还包括：用于识别和比较所选行地址（ADr）的至少一个电路 ），包括在所述关联存储器矩阵（14）中的有缺陷的行地址（ADrr），以便在有效识别的情况下产生故障行的选择和对应的冗余单元行的选择;以及至少一个配置 （17），还包括非易失性存储器单元矩阵和相关联的控制电路。

公开(公告)号：EP1031991A1

公开(公告)日：2000-08-30

申请号：EP99830108.9

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C11/56

CPC classification number: G11C11/5642

Abstract: The sensing circuits (30, 31, 32) comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit (32) associated with the lowest reference current (I R3 ) amplifies (33b) the cell current more than the other sensing circuits (30, 31) and to the respective reference current (33c). The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current (I R3 ) may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution (I M3 ), retaining the possibility of discriminating between the different logic levels.

Abstract translation: 比较在与参考电流的多个单元中流动的电流的感测电路（30，31，32）不彼此相同，但不同的扩增相比电流。 特别地，感测电路（32）具有最低的参考电流（IR3）放大相关联的（图33B）比其它感测电路的单元电流多（30，31）和所述respectivement参考电流（33C）。 当前动态由此增加，并且能够维持读取电压低，由于最低参考电流（IR3）的固有特性可以是非常靠近或直接叠加在做了立即preceding-存储器单元电流分布的（IM3） ，保持不同的逻辑电平之间进行区分的可能性。

公开(公告)号：EP0961285A1

公开(公告)日：1999-12-01

申请号：EP98830333.5

申请日：1998-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maurelli, Alfonso

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/06 ,  G11C7/062

Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

Abstract translation: 读取方法包括以下步骤：同时提供两个存储相应的未知充电条件的存储单元（F1，F2） 产生两个电量（Va，Vb），每个电量与相应的充电条件相关; 将两个电量（Va，Vb）彼此进行比较; 并根据比较结果生成2比特信号（01,02）。 读取电路包括并联的两个分支的双输入比较器（58），每个分支通过电流/电压转换器（41）连接到相应的存储单元。 双输入比较器（58）和电流/电压转换器（41）都包括低阈值晶体管（49,50,65-68）。

公开(公告)号：EP0928003A2

公开(公告)日：1999-07-07

申请号：EP98114061.9

申请日：1998-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read.
The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

Abstract translation: 本发明涉及一种用于电子存储单元装置的行解码电路，特别是在低电源电压应用中，其适用于通过至少一个升压电容器（Cboost）来升压要施加到存储器列的读取电压 包含要读取的存储单元。 电路在第一电源电压基准（Vpcx）和第二接地电位基准（GND）之间供电，并且包括级联连接的逆变器（15,16）的分级结构（13）和逐渐提高读取电压的电路装置 动态级别。 第一装置（Cboost0，D1）被提供用于将读取电压电平升高到等于电源电压（Vpcx）加上阈值电压（Vtp）的值，并且提供第二装置（Cboost1，D2）以提高读取电压电平 达到等于电源电压（Vpcx）加上两倍阈值电压（Vtp）的值。

公开(公告)号：EP0915476A1

公开(公告)日：1999-05-12

申请号：EP97830573.8

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Zammattio, Matteo ,  Ferrario, Donato

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier.
The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract translation: 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便也产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。

公开(公告)号：EP1837993B1

公开(公告)日：2010-01-27

申请号：EP06111477.3

申请日：2006-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

公开(公告)号：EP1837880B1

公开(公告)日：2009-08-26

申请号：EP06113480.5

申请日：2006-05-04

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C8/08 ,  G11C16/12

CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

公开(公告)号：EP1830269B1

公开(公告)日：2009-05-13

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18