公开(公告)号：JP2000269309A

公开(公告)日：2000-09-29

申请号：JP7587799

申请日：1999-03-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHOU CHII-HON ,  RUU UEN-CHOAN

IPC: H01L21/683 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide a mounting device of a structure, wherein a semiconductor wafer having one linear edge is not only made horizontally fixed but also prevented from being damaged on the corners of the wafer. SOLUTION: This device is a mounting device for fixing a semiconductor wafer, which consists of a round base to be mounted with the wafer and a round clamp consisting of a round aperture 28 having a plurality of teeth provided at equal intervals, on the peripheral side of the aperture 28 for fixing the wafer on the base by applying a pressure under the lower part of the water, when the wafer is mounted on the base and has one linear edge.

公开(公告)号：JP2000216239A

公开(公告)日：2000-08-04

申请号：JP961599

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO MASUTAMI ,  YEW TRI-RUNG ,  RO KATETSU

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To prevent the copper atoms sputtered during bombardment process from diffusing into a inter-metal dielectrics layer, by forming a barrier layer on a copper layer which is exposed at the bottom part of a via opening before bombardment process is performed with the bottom part of the via opening until the copper layer is exposed. SOLUTION: A barrier layer 322 is formed on a surface comprising the inside surfaces of groove openings 318a and 318b, the inside surface of a via opening 312a, and the surface of a copper oxide layer 320. Then bombardment process 324 is performed. Copper atoms 304 ejected from a copper layer 304 under the bombardment process 324 are prevented from diffusing inside a first dielectrics layer 306 by the presence of a barrier layer 322b on the side wall. A barrier layer 322 at the bottom part of the via opening 312a is removed. Then a groove 318 and the via opening 312a are filled by vapor-deposition of a conductor layer 326. The conductor layer 326 is directly connected to the copper layer 304. Thus, the copper atoms cannot diffuse into a dielectrics layer, while the resistance of a via plug is lowered.

公开(公告)号：JP2000216137A

公开(公告)日：2000-08-04

申请号：JP983499

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO ROSHO ,  FU KANYU

IPC: H01L21/302 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/822 ,  H01L27/04 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To protect a device against damage caused by plasma charge by a method wherein an inner dielectric layer, a conductive layer and an insulating layer are patterned for forming a contact opening that exposes a source/drain region, and the contact opening is provided with a side wall that exposes the conductive layer. SOLUTION: An ILD layer 210a, a conductive layer 208a and an insulating layer 206a are patterned through, for instance, a dry etching method to form a contact opening 212. The contact opening exposes the side wall 214 of the conductive layer 208a besides a doped region 204. As a result, excess charges produced during a plasma operation (e.g. PECVD or HDPCVD for forming an ILD layer 210) are channeled away through the conductive layer 208, so that an electric potential is adjusted, and the device can be protected against damage caused by a current flow toward potential gradient.

公开(公告)号：JP2000202262A

公开(公告)日：2000-07-25

申请号：JP1060999

申请日：1999-01-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO MEISEI ,  LAI CHIEN-HSIN ,  CHO KAZUI ,  WU JUAN-YUAN

IPC: B24B57/02 ,  B01F5/00 ,  B01F5/06 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a in situ mixing device improved in the mixing degree of slurry and capable of uniformly mixing. SOLUTION: The device has plural 1st tubes 104 each having a 1st diameter and plural 2nd tubes 102 each having a 2nd diameter, and is composed of a cylindrical main body 105 structured by alternately linking the 2nd tubes 102 and the 1st tubes 104 to each other and plural tapered plugs 103, and each of plural tapered plugs 103 is positioned inside each 2nd tube 103 and the tip part of the plug 103 face to the direction opposed to the flowing direction of fluid flowing in the cylindrical main body 105.

公开(公告)号：JP2000198061A

公开(公告)日：2000-07-18

申请号：JP164299

申请日：1999-01-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN JUEN-KUEN ,  LAI CHIEN-HSIN ,  PENG PENG-YIH ,  YO SHUKO ,  GO KONRIN ,  YU FUKUYO

IPC: B24B37/26 ,  B24D13/12 ,  B24D13/14 ,  H01L21/304 ,  B24B37/00

Abstract: PROBLEM TO BE SOLVED: To uniformly distribute the slurry to accelerate the polishing by designing a pattern of stream line grooves on a chemical mechanical polishing pad on the basis of a flow equation obtained from the blowout flow and the vortex flow. SOLUTION: The direction of a slurry flow includes the blowout flow and the vortex flow mentioned in an equation (I). In the equation I, Ψ is a stream line function, m is a strength parameter of blowout flow, k is a strength parameter of vortex flow, ln is a natural logarithm, and r, θ and z are coordinate parameters. A stream line groove function of an equation II is obtained on the basis of the equation I. In the equation II, exp is an exponential function, and C1 = constant = exp (Ψ/k). A designed pattern of the stream line grooves formed on a polishing pad for slurry is obtained on the basis of the equation I. The polishing pad is designed on the basis of the optimum result of the stream line groove pattern. By the stream line grooves, the direction of the slurry current can be optimized, and the slurry can be uniformly distributed under a polishing head. Whereby the polishing effect and the flatness can be effectively improved.

公开(公告)号：JP2000164861A

公开(公告)日：2000-06-16

申请号：JP33598398

申请日：1998-11-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHIH HSUEH-HAO ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a gate oxide film of high reliability, wherein adverse effects from a natural oxide are eliminated. SOLUTION: A semiconductor substrate 100, wherein a natural oxide layer 102 is naturally generated is put in a furnace or an RTO chamber (rapid thermal oxidation chamber) and a hot hydrogen gas is introduced into the chamber so that the natural oxide layer 102 is deoxidized. After that, a gate oxide film is formed on the semiconductor substrate. Such semiconductor substrate as a gate oxide film 104a formed is moved into a reaction chamber by a vacuum transfer system, so that a polysilicon layer 106 is formed on the gate oxide film. Re generation of natural oxide layer is prevented, since no semiconductor substrate is exposed to an oxygen-contained atmosphere.

公开(公告)号：JP2000091538A

公开(公告)日：2000-03-31

申请号：JP32102298

申请日：1998-11-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YEW TRI-RUNG

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified manufacturing method by using tungsten nitride as an MIM(metal-insulator-metal) capacitor structure. SOLUTION: In the process of forming a DRAM capacitor, a tungsten nitride is used. A step for introducing nitrogen to a tungsten silicide layer 110b and the step for performing rapid heat processing in the presence of ammonia gas, so as to form a tungsten nitride layer 111 on the surface of the tungsten silicide layer 110b are provided. This manufacturing method is provided with the formation of the tungsten silicide layer 110b, after forming a part smaller than the bottom electrode of the capacitor from doped polysilicon and the formation of the tungsten nitride on the surface of the tungsten nitride layer 111.

公开(公告)号：JP2000058637A

公开(公告)日：2000-02-25

申请号：JP29390398

申请日：1998-10-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  SO CHIN ,  RO KATETSU

IPC: H01L21/76 ,  H01L21/3205 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To prevent a dishing phenomenon, etc., and to ensure the uniformity of the whole semiconductor substrate by a method wherein an insulating layer is polished preparatorily, the whole substrate is flattened efficiently, and mainly polished by an etch-back process for exposing a masking layer and a shallow trench insulating structure section is formed. SOLUTION: A masking layer 102 is made on the whole surface of the semiconductor substrate 100. The substrate 100 is etched, and shallow trenches 104 are formed. An insulating layer 106 is made on the whole surface of the substrate 100, and the trenches 104 are also filled with the insulating layer. A part of the insulating film 106 covering the masking layer 102 is polished preparatorily, and polished in an extent that the masking layer 102 is not exposed, and an insulating layer 106a is formed. The masking layer 102 is used as an etching stop layer, the insulating film 106a is removed by etching, the masking layer 102 is exposed, the insulating layers are left in the trenches 104, and the insulating layers are used as insulating layers 106b, the surfaces of the insulating layers 106b are flattened, and the insulating layers 106b are formed in shallow trench insulating structure sections.

公开(公告)号：JP2000049228A

公开(公告)日：2000-02-18

申请号：JP30226498

申请日：1998-10-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene (dual etching decorative patterns) structure that is made of a material, having superior heat transfer action and accelerates semiconductor device operation. SOLUTION: This dual-damascene structure has a semiconductor substrate 210, a metal-oxide-semiconductor(MOS) transistor formed on this substrate and a metal layer. The metal layer is electrically connected to the conductive region 215 of the MOS transistor via a mutual connection part 218. Furthermore, the metal layer contains a first inter-metal region 240 and a second inter-metal region 250. The width of the first inter-metal region is about 1 to 10 times greater than that of the manufacturing line of the semiconductor device. The width of the second inter-metal layer is about 0.8 to 1.2 times greater than that of the manufacturing line. The first inter-metal region contains a dielectric 270 with a high dielectric constant to increase the heat transfer rate. The second inter-metal region contains a dielectric 280 with a low dielectric constant for shortening the resistance-capacitance delay.

公开(公告)号：JP2000031389A

公开(公告)日：2000-01-28

申请号：JP30432998

申请日：1998-10-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIOU FU-TAI

IPC: H01L27/04 ,  C22B5/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To form a resistor in an integrated circuit without using a polysilicon, by converting a selected part of a heat-resistant metal oxide layer into a conductive oxide of a specific resistance characteristics which acts as a desired resistor. SOLUTION: Firstly, a heat-resistant metal oxide layer 101 is formed on a substrate 100. Then, a mask layer 102 such as a photo-resist layer or a diffusion barrier layer is formed on the heat-resistant metal oxide layer 101. The mask layer 102 is selectively removed to form a contact hole 103 at the mask layer 102, so that the selected part 101a of the heat-resistant metal oxide layer 101 is exposed. Then a wafer 100 is oxygen-plasma processed or oxygen-thermal processed through the mask layer 102 so that the part 101a which is not masked is converted to a conductive oxide of a specific resistance characteristics. When the entire mask layer 102 is removed, the conductive oxide 101a of the heat- resistant metal oxide 101 functions as a desired resistor.