公开(公告)号：EP3409639A1

公开(公告)日：2018-12-05

申请号：EP18174480.6

申请日：2018-05-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： FUJII, Hidetoshi

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00587 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2201/0198 ,  B81C2201/053

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

公开(公告)号：EP2386521B1

公开(公告)日：2018-06-13

申请号：EP11161590.2

申请日：2011-04-08

Applicant: Omron Corporation

Inventor： Kasai, Takashi ,  Iida, Nobuyuki ,  Nakamura, Tomofumi

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0016 ,  B81B2201/0257 ,  B81B2207/012 ,  B81C2201/053 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/8592 ,  H01L2924/16151 ,  H04R19/005 ,  H04R31/00 ,  H01L2924/00014

Abstract: This invention aims to protect an outer peripheral part of an upper surface of a silicon substrate with a protective film using a back plate. A conductive diaphragm (33) is arranged on an upper side of a silicon substrate (32) including a back chamber (35), and the diaphragm (33) is supported with an anchor (37). An insulating plate portion (39) is fixed to an upper surface of the silicon substrate (32) so as to cover the diaphragm (33) with a gap. A conductive fixed electrode film (40) is arranged on a lower surface of the plate portion (39) to configure a back plate (34). The change in electrostatic capacitance between the fixed electrode film (40) and the diaphragm (33) is outputted to outside from a fixed side electrode pad (45) and a movable side electrode pad (46) as an electric signal. A protective film (53) is arranged in continuation to the plate portion (39) at an outer periphery of the plate portion (39), which protective film (53) covers the outer peripheral part of the upper surface of the silicon substrate (32) and the outer periphery of the protective film (53) coincides with the outer periphery of the upper surface of the silicon substrate (32).

公开(公告)号：EP3135631A1

公开(公告)日：2017-03-01

申请号：EP15382430.5

申请日：2015-08-24

Applicant: Graphenea, S.A.

Inventor： ZURUTUZA ELORZA, Amaia ,  CENTENO PÉREZ, Alba

IPC: B81C1/00

CPC classification number: B81C1/00158 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0191 ,  B81C2201/053 ,  C01B32/194

Abstract: A method of transferring graphene onto a target substrate having cavities and/or holes or onto a substrate having at least one water soluble layer is disclosed. It comprises the steps of: applying a protective layer (4) onto a sample comprising a stack (20) formed by a graphene monolayer (2) grown on a metal foil or on a metal thin film on a silicon substrate (1); attaching to said protective layer (4) a frame (5) comprising at least one outer border and at least one inner border, said frame (5) comprising a substrate and a thermal release adhesive polymer layer, the frame (5) providing integrity and allowing the handling of said sample; removing or detaching said metal foil or metal thin film on a silicon substrate (1); once the metal foil or metal thin film on a silicon substrate (1) has been removed or detached, drying the sample; depositing the sample onto a substrate (7); removing said frame (5) by cutting through said protective layer (4) at said at least one inner border of the frame (5) or by thermal release.

Abstract translation: 公开了一种将石墨烯转移到具有空穴和/或孔的目标基底上或具有至少一个水溶性层的基底上的方法。 其包括以下步骤：将保护层（4）施加到包含由在金属箔上生长的石墨烯单层（2）或在硅衬底（1）上的金属薄膜上形成的堆叠（20）的样品上; 附接到所述保护层（4）的框架（5）包括至少一个外边界和至少一个内边界，所述框架（5）包括基底和热释放粘合剂聚合物层，所述框架（5）提供完整性和 允许处理所述样品; 在硅衬底（1）上移除或分离所述金属箔或金属薄膜; 一旦硅衬底（1）上的金属箔或金属薄膜已经被去除或分离，干燥样品; 将样品沉积到衬底（7）上; 通过在框架（5）的所述至少一个内边界处切割所述保护层（4）或通过热释放来移除所述框架（5）。

公开(公告)号：EP2078694A3

公开(公告)日：2013-06-26

申请号：EP08105987.5

申请日：2008-12-16

Applicant: ROBERT BOSCH GMBH

Inventor： Teeffelen, Kathrin ,  Feyh, Ando ,  Leinenbach, Christina

IPC: B81C1/00

CPC classification number: B81C1/00896 ,  B81B2201/0257 ,  B81C2201/053

Abstract: Die Erfindung betrifft ein Schutzsystem für MEMS-Strukturen, mit einer fragilen offenen Struktur (12) und einer optionalen Opferschicht (13), aufgebracht auf einem Wafer (14), bei dem eine Schutzschicht (10) auf der Vorderseite der Struktur (12) aufgebracht ist, wobei die Schutzschicht (10) rückstandsfrei entfernbar ist, sowie ein Verfahren zur Vereinzelung von fragilen offenen MEMS-Strukturen.

公开(公告)号：EP2191503A1

公开(公告)日：2010-06-02

申请号：EP08786380.9

申请日：2008-07-24

Applicant: Robert Bosch GmbH

Inventor： KRAMER, Torsten ,  BOEHRINGER, Matthias ,  PINTER, Stefan ,  BENZEL, Hubert ,  ILLING, Matthias ,  HAAG, Frieder ,  ARMBRUSTER, Simon

IPC: H01L21/78 ,  B81C1/00

CPC classification number: H01L21/78 ,  B81C1/00896 ,  B81C2201/053

Abstract: The present invention proposes a production method for chips in which as many method steps as possible are carried out in the wafer assemblage, that is to say in parallel for a multiplicity of chips arranged on a wafer. This concerns a method for producing a multiplicity of chips whose functionality is realized on the basis of the surface layer (2) of a substrate (1). In this method, the surface layer (2) is patterned and at least one cavity (3) is produced below the surface layer (2) such that the individual chip regions (5) are interconnected and/or connected to the rest of the substrate (1) merely by means of suspension webs, and/or such that the individual chip regions (5) are connected to the substrate layer (4) below the cavity (3) by means of supporting elements (7) in the region of the cavity (3). The suspension webs and/or supporting elements (7) are separated during singulation of the chips. According to the invention, the patterned and undercut surface layer (2) of the substrate (1) is embedded into a plastics composition (10) before the singulation of the chips.

公开(公告)号：EP1853514A1

公开(公告)日：2007-11-14

申请号：EP05823865.0

申请日：2005-12-21

Applicant: ROBERT BOSCH GMBH

Inventor： ILLING, Matthias ,  WEBER, Heribert ,  SCHELLING, Christoph ,  STAHL, Heiko ,  WEISS, Stefan

IPC: B81B3/00

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C1/00476 ,  B81C2201/0109 ,  B81C2201/053

Abstract: The invention relates to a method for producing a micromechanical membrane sensor or a membrane sensor produced by means of said method. According to the invention, the micromechanical membrane sensor comprises at least one first membrane and a second membrane arranged essentially above the first membrane. Furthermore, the micromechanical membrane sensor comprises a first cavity and a second cavity arranged essentially above the first cavity.

公开(公告)号：EP1111671A3

公开(公告)日：2004-05-12

申请号：EP00127180.8

申请日：2000-12-12

Applicant: Micronas GmbH

Inventor： Igel, Günter, Dipl.-Ing.

IPC: H01L21/78 ,  B81C1/00

CPC classification number: B81C1/00904 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/78 ,  H01L23/3171 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

Abstract: Ein Verfahren dient zum Herstellen einer Halbleiteranordnung (3), wobei insbesondere ein Wafer (1) mit einer Vielzahl von Chips (7) bildenden Halbleiteranordnungen hergestellt und der Wafer danach zerteilt und dadurch die Halbleiteranordnungen vereinzelt werden. Zumindest ein Bereich einer Waferseite wird während des Ätzens des übrigen Waferbereichs mittels einer Passivierungsschicht (9) abgedeckt. Nach dem Ätzen wird dann die Passivierungsschicht (9) entfernt. Zumindest in einem äußeren Randbereich des Wafers, gegebenenfalls zusätzlich im Verlauf der Wafer-Vorderseite, außerhalb der aktiven Chipfläche und insbesondere in den die jeweiligen Chipsysteme umgrenzenden Bereichen werden Haftzonen (8) für die Passivierungsschicht (9) geschaffen, die mit dem für die Passivierungsschicht verwendeten Material eine dichtende, insbesondere chemische Verbindung eingehen. Außerhalb der Haftzonen ist eine verminderte Haftfähigkeit vorhanden, so dass die Passivierungsschicht (9) zum Beispiel nach dem Rückseitenätzen in dem außerhalb der Haftzonen (8) liegenden Bereich mechanisch durch einen Flüssigkeitsstrom und/oder durch einen Gasstrom und/oder durch Ultraschallbeaufschlagung von der Waferoberfläche entfernt werden kann.

公开(公告)号：EP0922944B1

公开(公告)日：2003-08-27

申请号：EP98830266.7

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

IPC: G01L9/00

CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

公开(公告)号：EP1245528A1

公开(公告)日：2002-10-02

申请号：EP01610035.6

申请日：2001-03-27

Applicant: Delta Danish Electronics, Light & Acoustics

Inventor： Lisby, Torben ,  Branebjerg, Jens A.

IPC: B81B3/00 ,  B81B7/00 ,  G02B6/42 ,  B01L3/00

CPC classification number: G02B6/4226 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/123 ,  B81C1/0019 ,  B81C2201/017 ,  B81C2201/053 ,  B81C2203/0136 ,  G02B6/3502 ,  G02B6/3584

Abstract: The present invention relates to microsystems having flexibility properties so as to enable folding of the microsystem in any three-dimensional direction. That is, enabling torsional and three-dimensionally non-linearly bending of the microsystem. The present invention provides a flexible three-dimensional microsystem compatible with hostile environments such as encountered within a biological body. In particular, provides a bio-compatible three-dimensional microsystem operational in hostile environments while biological acceptable to biological bodies. The present invention further provides an overall stress stability since forming a unitary structure eliminating stress induced or caused by joining various parts of different materials having different material properties into an assembly.

Abstract translation: 本发明涉及具有柔性的微系统，以便能够在任何三维方向折叠微系统。 也就是说，实现微系统的扭转和三维非线性弯曲。 本发明提供了一种灵活的三维微系统，与诸如在生物体内遇到的敌对环境兼容。 特别地，提供了生物相容性的三维微系统在敌对环境中运行，而生物体可接受生物体。 本发明进一步提供了整体应力稳定性，因为形成一体结构，消除了将具有不同材料特性的不同材料的各种部件接合到组件中而引起或引起的应力。

公开(公告)号：EP1161985A1

公开(公告)日：2001-12-12

申请号：EP00830400.8

申请日：2000-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele ,  Cattaneo, Mauro

IPC: B01J19/00

CPC classification number: B81C1/00119 ,  B01J19/0093 ,  B01L3/5027 ,  B01L3/502707 ,  B01L7/52 ,  B01L7/525 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/1827 ,  B01L2300/185 ,  B01L2300/1883 ,  B81B2201/0214 ,  B81B2201/051 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/053

Abstract: The microreactor is completely integrated and is formed by a semiconductor body (2) having a surface (4) and housing at least one buried channel (3) accessible from the surface of the semiconductor body (2) through two trenches (21a, 21b). A heating element (10) extends above the surface (4) over the channel (3) and a resist region (18) extends above the heating element and defines an inlet reservoir and an outlet reservoir (19, 20). The reservoirs (19, 20) are connected to the trenches (21a, 21b) and have, in cross-section, a larger area than the trenches. The outlet reservoir (20) has a larger area than the inlet reservoir (19). A sensing electrode (12) extends above the surface (4) and inside the outlet reservoir (20).

Abstract translation: 微反应器是完全呼叫集成并且由一个半导体主体（2）形成具有表面（4）和壳体的至少一个掩埋沟道（3）从所述半导体主体（2）的表面通过两个沟槽访问（21A，21B） ， 的加热元件（10）的表面（4）在所述通道（3）和抗蚀剂区域（18）上方延伸，加热元件的上方延伸，并且限定到入口储槽和出口储槽（19，20）。 储存器（19，20）连接到所述沟槽（21A，21B），并且具有，在横截面中，比沟槽更大的面积。 出口储槽（20）具有比所述入口储（19）大的面积。 的感测电极（12）的表面（4）的上方和出口储槽（20）的内部延伸。