公开(公告)号：US20070167036A1

公开(公告)日：2007-07-19

申请号：US11652818

申请日：2007-01-12

Applicant: Ock-Jin Kim

Inventor： Ock-Jin Kim

IPC: H01R12/00

CPC classification number: G09G3/3611 ,  G02F1/13452 ,  G09G2320/0223 ,  H01R12/7076 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10674

Abstract: A flexible circuit board includes a base substrate, a driving chip, an input transmission line, an output transmission line and a connecting transmission line. The driving chip is on a surface of the base substrate. The input transmission line is on the surface of the base substrate and electrically connected to an input terminal of the driving chip. The output transmission line is on the surface of the base substrate and electrically connected to an output terminal of the driving chip. The input transmission line is electrically connected to the output transmission line through the connecting transmission line.

Abstract translation: 柔性电路板包括基底基板，驱动芯片，输入传输线，输出传输线和连接传输线。 驱动芯片在基底基板的表面上。 输入传输线在基板的表面上，并与驱动芯片的输入端电连接。 输出传输线位于基底表面上，并与驱动芯片的输出端电连接。 输入传输线通过连接传输线电连接到输出传输线。

公开(公告)号：US07105923B2

公开(公告)日：2006-09-12

申请号：US10103386

申请日：2002-03-21

Applicant: Kevin P. Lyne

Inventor： Kevin P. Lyne

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

公开(公告)号：US20060163721A1

公开(公告)日：2006-07-27

申请号：US11040726

申请日：2005-01-21

Applicant: Frederick Kuhlman ,  Brentt Duff ,  Michael Pepples ,  Raymond Anton ,  Daniel Harshbarger

Inventor： Frederick Kuhlman ,  Brentt Duff ,  Michael Pepples ,  Raymond Anton ,  Daniel Harshbarger

IPC: H01L23/10

CPC classification number: H05K3/3452 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K2201/09772 ,  H05K2201/09909 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic assembly includes a substrate and at least one surface mounted electronic component. The substrate includes a first side and a second side opposite the first side. The first side of the substrate includes a plurality of conductive traces formed thereon. The plurality of conductive traces includes a first conductive trace and a second conductive trace. The electronic component is electrically coupled between the first and second conductive traces. A component body of the electronic component is subject to interaction with a flux, which is utilized during electrical coupling of the electronic component to the first and second conductive traces, to form a current leakage path. The substrate is configured to prevent the formation of the current leakage path.

Abstract translation: 电子组件包括基板和至少一个表面安装的电子部件。 基板包括与第一侧相对的第一侧和第二侧。 基板的第一面包括形成在其上的多个导电迹线。 多个导电迹线包括第一导电迹线和第二导电迹线。 电子部件电耦合在第一和第二导电迹线之间。 电子部件的组件主体经受与焊剂的相互作用，焊剂在电子部件与第一和第二导电迹线的电耦合期间被利用，以形成电流泄漏路径。 衬底被配置为防止形成电流泄漏路径。

公开(公告)号：US20040251533A1

公开(公告)日：2004-12-16

申请号：US10813137

申请日：2004-03-29

Inventor： Takeshi Suzuki ,  Kazushige Osumi ,  Junichi Ichihashi ,  Toshiyuki Iimura ,  Shinichi Tsuyuki

IPC: H01L023/48 ,  H01L023/52

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/09772 ,  H05K2201/10287 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided is a hybrid integrated circuit device which can more effectively stabilize a circuit configured to operate at a high speed. A hybrid integrated circuit device of the embodiment includes a metal substrate provided with an insulating layer on a surface thereof, a conductive pattern formed on a surface of the insulating layer, a semiconductor element fixed onto the conductive pattern, a lead as external connecting means fixed to the conductive pattern in the periphery of the metal substrate, and a contact portion for electrically connecting the conductive pattern electrically connected to the semiconductor element to the metal substrate in the vicinity of the semiconductor element.

Abstract translation: 提供了一种混合集成电路器件，其可以更有效地稳定被配置为高速操作的电路。 本实施例的混合集成电路器件包括在其表面上设置有绝缘层的金属基板，形成在绝缘层的表面上的导电图案，固定到导电图案上的半导体元件，固定的外部连接装置的引线 涉及金属基板周边的导电图案，以及用于将与半导体元件电连接的导电图案与半导体元件附近的金属基板电连接的接触部。

公开(公告)号：US06803664B2

公开(公告)日：2004-10-12

申请号：US10123211

申请日：2002-04-17

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2940

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10318 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

公开(公告)号：US06657275B1

公开(公告)日：2003-12-02

申请号：US09366439

申请日：1999-08-02

Applicant: Chee-Yee Chung ,  David G. Figueroa ,  Yuan-Liang Li

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Yuan-Liang Li

IPC: H01L2900

CPC classification number: H05K1/113 ,  H01L23/5222 ,  H01L23/5286 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K2201/09309 ,  H05K2201/09381 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Abstract translation: 集成电路封装和接地侧电容器，具有降低的功率输出环路电感。 电容器垫具有位于陆侧电容器下面的通孔，并且具有插入的数字。

公开(公告)号：US20030053296A1

公开(公告)日：2003-03-20

申请号：US10096509

申请日：2002-03-13

Applicant: Fujitsu Limited

Inventor： Atsuko Tanaka ,  Masuo Ohnishi

IPC: H05K005/00

CPC classification number: H05K1/0272 ,  G06F1/203 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.

Abstract translation: 风扇单元的风扇壳体包括从印刷电路板的表面竖立的壳体壁。 印刷电路板用于与壳体壁一起建立风扇壳体。 风扇壳体还包括连接到壳体壁的顶壁。 顶壁沿平行于印刷电路板表面的基准平面延伸。 风扇外壳内可能产生高速气流。 气流促进印刷电路板的热辐射。 在印刷电路板的表面上延伸的导电布线图形可以进一步促进来自印刷电路板的热辐射。

公开(公告)号：US20030033108A1

公开(公告)日：2003-02-13

申请号：US10029571

申请日：2001-12-20

Inventor： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

IPC: G06F019/00

CPC classification number: G06F17/5068 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09627 ,  H05K2201/09772 ,  H05K2201/10151

Abstract: A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

Abstract translation: 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

公开(公告)号：US20010024360A1

公开(公告)日：2001-09-27

申请号：US09800582

申请日：2001-03-08

Applicant: FUJI XEROX CO., LTD.

Inventor： Masayuki Hirata ,  Osamu Ueno

IPC: H05K007/02

CPC classification number: H05K9/0039 ,  H05K1/0225 ,  H05K1/0233 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689

Abstract: A printed wiring board in which noise components at a high frequency side of a power supply voltage can be eliminated, and undesired radiation noisewhich is newly generated can be suppressed, such that noise can be greatly reduced overall. The printed wiring board includes a first signal layer, a GND layer, a power source layer and a second signal layer. A sub-power source layer is provided on a same layer as a main power source layer. The sub-power source layer is formed in a substantially oval shape at a predetermined position in a substantially oval opening in the main power source layer, such that it is not in direct contact with the main power source layer. Power supply voltage is supplied from the main power source layer through an L-type filter.

Abstract translation: 可以抑制能够消除电源电压的高频侧的噪声成分的新印刷布线板，并且可以抑制新生成的不期望的放射线，使得整体上可以大大降低噪声。 印刷电路板包括第一信号层，GND层，电源层和第二信号层。 子电源层设置在与主电源层相同的层上。 子电源层在主电源层中的大致椭圆形的开口中的预定位置处形成为大致椭圆形状，使得它不与主电源层直接接触。 电源电压由主电源层通过L型滤波器供电。

公开(公告)号：US5892274A

公开(公告)日：1999-04-06

申请号：US900243

申请日：1997-07-24

Applicant: Milton L. Buschbom

Inventor： Milton L. Buschbom

IPC: H01L23/16 ,  H01L23/433 ,  H05K1/02 ,  H01L23/48 ,  H01L29/40 ,  H01L39/00

CPC classification number: H05K1/0243 ,  H01L23/16 ,  H01L23/4334 ,  H05K1/0218 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/10689

Abstract: The invention is to a combination of a semiconductor device and a ground plane on a printed wiring board to provide a controlled impedance signal lead. A printed wiring board has a ground plane layer, and a semiconductor device having a down-set, or deep down-set, lead frame die mounting pad is mounted on the printed wiring board above the ground plane layer. The leads of the semiconductor device form a transmission line in combination with the ground plane, when the leads are placed a controlled distance above the ground plane.

Abstract translation: 本发明是在印刷电路板上的半导体器件和接地平面的组合，以提供受控的阻抗信号引线。 印刷电路板具有接地层，并且在接地层上方的印刷电路板上安装有具有下降或下降的引线框模具安装焊盘的半导体器件。 当引线被放置在接地平面上方受控的距离时，半导体器件的引线与接地平面组合形成传输线。