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公开(公告)号：KR1020170000421A
公开(公告)日：2017-01-03
申请号：KR1020150088939
申请日：2015-06-23
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L29/66
Abstract: 반도체소자의기판상의소스전극들및 드레인전극들은기판의상면에평행한제1 방향및 제1 방향과교차하는제2 방향을따라교대로배열되고, 소스배선들은소스전극들상에서, 소스전극들과전기적으로연결되고, 드레인패드는소스배선들상에서, 드레인전극들과전기적으로연결되고, 소스배선들은소스전극들상에서교차점을갖는그리드(grid) 형상을갖고, 평면적관점에서, 드레인패드는소스전극들및 드레인전극들과중첩된다.
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公开(公告)号：KR1020150066853A
公开(公告)日：2015-06-17
申请号：KR1020130152420
申请日：2013-12-09
Applicant: 한국전자통신연구원
IPC: H01L33/00 , H01L33/32 , H01L21/205 , H01L21/02 , H01L21/28
CPC classification number: H01L33/0075 , H01L21/0228 , H01L21/02293 , H01L21/2056 , H01L21/28194 , H01L33/0062 , H01L33/32
Abstract: 본발명은질화물반도체의제조방법에관한것으로, 반응기내에기판을준비하는것 및상기기판상에에피층을형성하는것을포함하고, 상기에피층을형성하는것은펄스플로우성장법을수행하는것을포함하되, 상기펄스플로우성장법은상기기판상에 5족소스물질을공급하는것 및상기기판상에 3족소스물질을공급하는것을포함하고, 상기 5족및 3족소스물질들은상기반응기내에교대로공급되되, 상기 5족소스물질은히드라진(hydrazine) 계열의물질을포함하는질화물반도체의제조방법에제공된다.
Abstract translation: 本发明涉及一种用于制造氮化物半导体的方法，包括在反应器中制备衬底并在衬底上形成外延层的步骤。 形成外延层时进行脉冲流生长方法; 脉冲流生长方法包括在基板上提供3-5组源材料; 将组3-5材料交替地供应到反应器的内部; 5组源材料包括肼类材料。
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公开(公告)号：KR1020140078185A
公开(公告)日：2014-06-25
申请号：KR1020120147251
申请日：2012-12-17
Applicant: 한국전자통신연구원
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: An electronic chip and a method of fabricating the same are provided. A semiconductor chip may include a substrate; an active device integrated with the substrate; a lower interlayer dielectric which covers the front surface of the result where the active device is provided, and a passive device provided on the lower interlayer dielectric; an upper interlayer dielectric which covers the front surface of the result where the passive device is provided; and a ground electrode provided on the upper interlayer dielectric. In this case, the upper interlayer dielectric layer is made of a material whereby the dielectric constant is higher than that of the lower interlayer dielectric.
Abstract translation: 提供电子芯片及其制造方法。 半导体芯片可以包括基板; 与衬底集成的有源器件; 覆盖提供有源器件的结果的前表面的下层间电介质和设置在下层间电介质上的无源器件; 覆盖提供无源器件的结果的前表面的上层间电介质; 以及设置在上层间电介质上的接地电极。 在这种情况下，上层间电介质层由介电常数高于下层间电介质的材料制成。
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公开(公告)号：KR1020110049255A
公开(公告)日：2011-05-12
申请号：KR1020090106191
申请日：2009-11-04
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A method for manufacturing a semiconductor substrate for a semiconductor light emitting device and method for manufacturing a semiconductor light emitting device are provided to reduce stress due to mismatch of grid coefficients and thermal expansion coefficients between a silicon substrate and a GaN semiconductor film, thereby increasing light extracting efficiency. CONSTITUTION: An oxide layer(110) is formed on a silicon substrate. A metal thin film is deposited on the oxide layer. A metal thin fill is annealed to form a metal nano particle with a nano pattern. An oxide layer is etched by a nano pattern using the metal nano particle as a mask. The metal nano particle is etched. The oxide layer is etched by a nano pattern by using the metal nano particle as a mask. A buffer layer(130) is formed on an oxide layer and a silicon substrate on which an oxide layer is not formed.
Abstract translation: 目的：提供一种半导体发光器件用半导体衬底的制造方法及半导体发光元件的制造方法，以减少由于硅衬底与GaN半导体膜之间的栅格系数不匹配和热膨胀系数引起的应力，由此 提高光提取效率。 构成：在硅衬底上形成氧化物层（110）。 金属薄膜沉积在氧化物层上。 将金属薄填充物退火以形成具有纳米图案的金属纳米颗粒。 使用金属纳米颗粒作为掩模，通过纳米图案蚀刻氧化物层。 蚀刻金属纳米颗粒。 通过使用金属纳米颗粒作为掩模，通过纳米图案蚀刻氧化物层。 在氧化物层和未形成氧化物层的硅衬底上形成缓冲层（130）。
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公开(公告)号：KR1020100061607A
公开(公告)日：2010-06-08
申请号：KR1020080120192
申请日：2008-11-29
Applicant: 한국전자통신연구원
IPC: G02B6/10 , H01L27/146
CPC classification number: H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
Abstract: PURPOSE: A high speed optical wiring element is provided to form an optical has high speed, low power, and low price without a serializer, a parallelizer, and a modulator by using a multi-channel fiber. CONSTITUTION: A first semiconductor chip(301) is formed on a SOI(Silicon On Insulator) substrate(200). An optical emitter(302) outputs a multiple optical signal by receiving a multiple electric signal from the first semiconductor chip on the SOI substrate. An optical detector(304) changes the multi optical signal of the SOI substrate into the multiple electric signal. A second semiconductor chip(305) receives a multiple electric signal transformed with the optical detector of the SOI substrate. The SOI substrate comprises a first SOI substrate, a second semiconductor chip, and a second SOI substrate. The first SOI substrate and the second SOI substrate are arranged to be separated.
Abstract translation: 目的：通过使用多通道光纤，提供高速光配线元件以形成具有高速度，低功率和低价格的光学，而不需要串行器，并行器和调制器。 构成：在SOI（绝缘体上硅）衬底（200）上形成第一半导体芯片（301）。 光发射器（302）通过从SOI衬底上的第一半导体芯片接收多个电信号来输出多个光信号。 光检测器（304）将SOI衬底的多光信号改变为多电信号。 第二半导体芯片（305）接收用SOI衬底的光检测器变换的多电信号。 SOI衬底包括第一SOI衬底，第二半导体芯片和第二SOI衬底。 第一SOI衬底和第二SOI衬底被布置成分离。
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Patent Agency Ranking
公开(公告)号：KR1020090059795A
公开(公告)日：2009-06-11
申请号：KR1020070126841
申请日：2007-12-07
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
CPC classification number: H01L21/76877 , H01L21/0274 , H01L21/31144 , H01L21/76802 , H01L21/76897
Abstract: A manufacturing method of a multilayer metal wiring is provided to stably manufacture a multilayer metal wiring and to reduce possibility of misalignment by forming a pattern through one exposure. A source drain ohmic metal layer is formed by depositing an ohmic metal(130) on a semiconductor substrate having an active layer and a cap layer. A first insulation film(140) is deposited on a whole surface of the semiconductor substrate. A first multilayer photoresist is deposited in consideration of an etching selection ratio with the first insulation film. A first metal wiring(170a) is formed by depositing a metal on a first pattern region. A second insulation film(180) is formed on a whole surface of the substrate having the first metal wiring. A second multilayer photoresist(150b,160b) is deposited in consideration of an etching selection ratio with the second insulation film. A second metal wiring(170b) is formed by depositing a metal on a second pattern region. A protective film is deposited on the second metal wiring.
Abstract translation: 提供多层金属布线的制造方法，以稳定地制造多层金属布线，并通过一次曝光形成图案来减少不对准的可能性。 源极欧姆金属层通过在具有有源层和盖层的半导体衬底上沉积欧姆金属（130）而形成。 第一绝缘膜（140）沉积在半导体衬底的整个表面上。 考虑到与第一绝缘膜的蚀刻选择比，沉积第一多层光致抗蚀剂。 通过在第一图案区域上沉积金属来形成第一金属布线（170a）。 在具有第一金属布线的基板的整个表面上形成第二绝缘膜（180）。 考虑到与第二绝缘膜的蚀刻选择比，沉积第二多层光致抗蚀剂（150b，160b）。 通过在第二图案区域上沉积金属来形成第二金属布线（170b）。 保护膜沉积在第二金属布线上。
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公开(公告)号：KR1020090059450A
公开(公告)日：2009-06-11
申请号：KR1020070126316
申请日：2007-12-06
Applicant: 한국전자통신연구원
IPC: H01P3/08
CPC classification number: H01P3/08 , H01P1/2136 , H01P5/19
Abstract: An ultra-high frequency transmitting device is provided to relieve discontinuity of electric field in a junction region between a strip transmission line and a micro strip transmission line by using a signal matching ground. An ultra-high frequency transmitting device includes a strip transmission line(strip), a micro strip transmission line(Mstrip), and a signal matching ground(Stuning). The strip transmission line is arranged inside a multilayer substrate. The micro strip transmission line is arranged outside the multilayer substrate. The micro strip transmission line is connected to the strip transmission line. The signal matching ground is positioned in a bottom surface of the micro strip transmission line. The signal matching ground is extended from the micro strip transmission line to the strip transmission line. The signal matching ground is connected to a ground(GND2) positioned in a bottom layer of the multilayer substrate.
Abstract translation: 提供了一种超高频发射装置，通过使用信号匹配地来缓解带状传输线和微带传输线之间的接合区域中的电场的不连续性。 超高频发送装置包括带状传输线（条），微带传输线（Mstrip）和信号匹配接地（Stuning）。 带状传输线设置在多层基板内。 微带传输线布置在多层基板的外侧。 微带传输线连接到条传输线。 信号匹配接地位于微带传输线的底面。 信号匹配接地从微带传输线延伸到带状传输线。 信号匹配地连接到位于多层基板的底层中的地（GND2）。
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公开(公告)号：KR100857469B1
公开(公告)日：2008-09-08
申请号：KR1020070025080
申请日：2007-03-14
Applicant: 한국전자통신연구원
Abstract: 본 발명은 밀리미터파 대역 전송특성을 향상시키기 위한 변환기가 구비된 초고주파 모듈에 관한 것으로, 마이크로스트립 전송선로와 CBCPW 전송선로를 와이어 본딩을 이용하여 연결할 경우, 와이어 본딩에 의한 임피던스 변화와 두 전송선로 사이의 전계성분의 급격한 변화를 변환기를 통해 완화시켜 삽입손실 및 반사손실이 감소되도록 함으로써, 밀리미터파 대역의 전송특성을 향상시키는 것을 특징으로 한다.
밀리미터파 대역, 와이어 본딩, 변환기, 마이크로스트립, CBCPW, SOP-
公开(公告)号：KR100576708B1
公开(公告)日：2006-05-03
申请号：KR1020030087994
申请日：2003-12-05
Applicant: 한국전자통신연구원
IPC: H01L27/095
CPC classification number: H01L29/7785
Abstract: 이중 면도핑 구조를 가지는 에피 기판으로부터 얻어진 고전력, 저삽입손실, 고격리도, 고스위칭속도를 갖는 고주파 스위치 소자에 관하여 개시한다. 본 발명에 따른 고주파 스위치 소자는, GaAs 반절연 기판 상에 AlGaAs/GaAs 초격자 버퍼층, 제1 Si 면도핑층, 도핑되지 않은 제1 AlGaAs 스페이서, 도핑되지 않은 InGaAs층, 도핑되지 않은 제2 AlGaAs 스페이서, 상기 제1 Si 면도핑층보다 큰 도핑 농도를 가지는 제2 Si 면도핑층 및 도핑되지 않은 GaAs/AlGaAs 캡층이 차례로 적층된 에피 기판을 포함한다. 상기 도핑되지 않은 GaAs/AlGaAs 캡층 위에는 상기 도핑되지 않은 GaAs/AlGaAs 캡층과 오믹 콘택을 형성하는 소오스 전극 및 드레인 전극이 형성되어 있다. 상기 소오스 전극 및 드레인 전극 사이에는 상기 도핑되지 않은 GaAs/AlGaAs 캡층과 쇼트키 콘택을 형성하는 게이트 전극이 형성되어 있다.
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公开(公告)号：KR100385856B1
公开(公告)日：2003-06-02
申请号：KR1020000082810
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L21/335
CPC classification number: H01L29/66848
Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.
Abstract translation: 本发明提供了一种自对准栅极晶体管。 本发明仅在具有离子注入沟道层的半导体衬底上的栅极下方的沟道区下方以及源极和漏极下方的P型杂质离子注入P型杂质离子，而不将P型杂质离子注入到源极栅极 和栅极 - 漏极，沉积栅极金属并蚀刻栅极图案。 在这种情况下，栅极的长度（Lg）被限定为比在沟道层下方注入P型杂质离子的长度（Lch-g）窄，因此改善了夹断特性。 根据本发明的制造具有自对准栅极的场效应晶体管的方法包括以下步骤：仅在栅极下面的沟道区下面以及源极和漏极下面注入P型杂质离子; 以及使用干蚀刻方法沉积具有良好高温稳定性的耐火栅极金属以形成栅极图案。
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