公开(公告)号：EP2241167A1

公开(公告)日：2010-10-20

申请号：EP08869756.0

申请日：2008-11-05

Applicant: Xilinx, Inc.

Inventor： DUONG, Anthony, T.

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/0262 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10212 ,  H05K2201/10734

Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes (1 -24) so as to minimize inductance between a FPGA (105) and PCB voltage planes (1 -24) for critical core voltages within the FPGA (105). Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

公开(公告)号：EP2140741A4

公开(公告)日：2010-09-15

申请号：EP07748420

申请日：2007-04-20

Applicant: ERICSSON TELEFON AB L M

Inventor： ENGBLOM LARS ,  JOHANSSON MATS ,  SCOTT PETER

IPC: H05K1/02 ,  H03K17/00

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09327

公开(公告)号：EP1715732A2

公开(公告)日：2006-10-25

申请号：EP06008023.1

申请日：2006-04-18

Applicant: ASUSTeK Computer Inc.

Inventor： Chen, Yueh-Chih ,  Chang, Kai-Shun

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0209 ,  H05K1/0206 ,  H05K1/0207 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09327

Abstract: A printed circuit board structure includes a signal reference layer (340) exposed at the surface of the printed circuit board (300). Through the large-area copper material of the signal reference layer (340) having a good heat conduction properties, the heat generated by thermal devices (360) located on the opposite surface of the printed circuit board (300), can be dissipated by convection in the environment surrounding the printed circuit board (300) to achieve a good heat dissipation effect.

Abstract translation: 的印刷电路板结构包括在所述印刷电路板（300）的表面露出的信号参考层（340）。 通过具有良好导热特性的信号的参考层（340）的大面积的铜材料，通过位于印刷电路板（300）的相对的表面上的热装置（360）产生的热量可以通过对流消散 在环境周围的印刷电路板（300），以达到良好的散热效果。

公开(公告)号：EP0600052B1

公开(公告)日：1996-04-17

申请号：EP93909756.4

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter ,  MARTINELLI, Marco

IPC: H05K3/40

CPC classification number: H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: The process for producing subsequently contactable contact points between two conductive track planes on a circuit substrate separated by an electrically insulating layer makes it possible to produce, for example, a basic conductor pattern which can subsequently be easily adapted to requirements. By laying windows in the conductive track planes out in such a way that, when the electrically insulating layer is subsequently through-etched due to under-etching, rod-like parts connected to the aperture periphery are revealed between or in the apertures which can be brought into contact with electrically conductive parts of the other conductive track plane, these conductive tracks can be electrically interconnected by mechanical bending.

公开(公告)号：EP0575292B1

公开(公告)日：1996-03-13

申请号：EP93810414.8

申请日：1993-06-09

Applicant: DYCONEX PATENTE AG

Inventor： Schmidt, Walter, Dr. ,  Martinelli, Marco

IPC: H05K3/00 ,  H05K3/42

CPC classification number: H05K3/42 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/4084 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

公开(公告)号：EP0186485A2

公开(公告)日：1986-07-02

申请号：EP85309399.5

申请日：1985-12-23

Applicant: FUJITSU LIMITED

Inventor： Kuwabara, Kiyoshi ,  Nishihara, Mikio ,  Tsunoi, Kazuhisa

IPC: H05K1/00

CPC classification number: H05K1/116 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09454

Abstract: A high density multilayer printed circuit board comprising signal layers (C), electric source layers (B), and ground layers (G), with insulating layers arranged between the signal layers and the electric source layers, between the electric source layers and the ground layers, and between the ground layers and the signal layers. Conductor portions (5a. 5b, 5c) forming through holes (6a, 6b, 6c) are opened in a perpendicular direction to the signal layers, electric source layers, and ground layers. The conductor portions are electrically connected to the signal layers and/or the electric source layers, and/or the ground layers, through lands (3a, 3b, 3c) thereof, the connections of the lands being substantially equally distributed among the conductor portions.

公开(公告)号：US20190230785A1

公开(公告)日：2019-07-25

申请号：US16224965

申请日：2018-12-19

Applicant: GigaLane Co., Ltd.

Inventor： Sang Pil Kim ,  Byung Hoon Jo ,  Da Yeon Lee ,  Byung Yeol Kim ,  Hee seok Jung

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0222 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09327

Abstract: In one example, a flexible circuit board includes a signal line disposed between a first ground and a second ground; a dielectric disposed between the first ground and the signal line and between the second ground and the signal line; and via holes formed by filling a plurality of holes, which are formed in a vertical direction such that the first ground and the second ground are electrically connected, with conductors, wherein the signal line is laterally bent so as to be spaced apart from positions where the via holes are formed.

公开(公告)号：US20180235076A1

公开(公告)日：2018-08-16

申请号：US15737876

申请日：2016-07-04

Applicant: NEC Corporation

Inventor： Kazuhiro KASHIWAKURA ,  Ayako UEMURA

IPC: H05K1/02 ,  H05K3/46 ,  H05K9/00 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/11 ,  H05K3/46 ,  H05K9/0064 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09609 ,  H05K2201/10

Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.Further, a printed board of the present invention includes a power supply layer disposed in a printed board and put between ground layers above and below the power supply layers, and a plurality of through holes connecting the ground layers above and below the power supply layers, wherein the plurality of the through holes are disposed at and near the power supply layer and are spaced apart at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.

公开(公告)号：US20180177040A1

公开(公告)日：2018-06-21

申请号：US15840598

申请日：2017-12-13

Applicant: Onkyo Corporation

Inventor： Makoto YOSHIDA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0225 ,  H05K1/0259 ,  H05K9/0039 ,  H05K9/006 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09354

Abstract: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.

公开(公告)号：US20140133115A1

公开(公告)日：2014-05-15

申请号：US13922349

申请日：2013-06-20

Applicant: FUJI XEROX Co., Ltd.

Inventor： Daisuke IGUCHI

IPC: H05K1/02

CPC classification number: H05K1/0243 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/162 ,  H05K1/181 ,  H05K2201/041 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.

Abstract translation: 多层布线板包括信号电极，第一电源电极和接地电极，它们连接到输出信号的第一元件，连接到接收信号的第二元件的电极，用作 用于所述信号的返回电流的返回路径，与所述接地层相邻设置有电介质层并且向所述第一元件提供电力的第一电源层和与所述第一电源层独立地设置的第二电源层， 第一电源层并且向第二元件供电。 第一电源层使返回电流通过第一电源电极返回到第一元件，作为接地层和第一电源层之间的位移电流。