公开(公告)号：EP3030058A3

公开(公告)日：2017-03-01

申请号：EP15197810.3

申请日：2015-12-03

Applicant: Automotive Lighting Reutlingen GmbH

Inventor： Temme, Jürgen ,  Schöning, Michael ,  Kutschat, Jürgen

IPC: H05K1/02

CPC classification number: H05K1/0206 ,  H05K1/0207 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10106

Abstract: Vorgestellt wird eine Leiterplatte für Kraftfahrzeugbeleuchtungseinrichtungen, die einen Schichtstapel mit mehreren Metallschichten und mehreren dielektrischen Schichten aufweist. Erste metallische Durchkontaktierungen dienen zur thermischen Verbindung einer dritten mit einer zweiten Metallschicht. Zweite metallische Durchkontaktierungen dienen zur thermischen Verbindung der zweiten und einer ersten Metallschicht. Die Beleuchtungseinrichtung zeichnet sich durch fünf erste Durchkontaktierungen und vier zweite Durchkontaktierungen aus, wobei vier erste Durchkontaktierungen Eckpunkte eines ersten Rechtecks bilden, die fünfte der ersten Durchkontaktierungen im Schnittpunkt der Diagonalen des ersten Rechtecks liegt, und die vier zweiten Durchkontaktierungen auf den Eckpunkten eines zweiten Rechtecks liegen, wobei jeweils ein Eckpunkt des zweiten Quadrats in der Mitte einer Seite des ersten Rechtecks liegt.

公开(公告)号：EP3035382A1

公开(公告)日：2016-06-22

申请号：EP15198089.3

申请日：2015-12-04

Applicant: University Of Windsor

Inventor： CHOWDHURY, Sazzadur

IPC: H01L23/15 ,  H01L23/552 ,  H01L23/66

CPC classification number: H05K3/4605 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/09609 ,  H01L2924/00

Abstract: An integrated circuit assembly which includes stacked printed ceramic substrate layers, and incorporates a shielding enclosure extending about the electrical conductor traces and interconnects which form the assembly circuitry. The shielding enclosure is configured to reduce electric and/or magnetic field leakage or interference with the traces and interconnects. The enclosure is provided as a cage about the assembly circuitry, and which is formed as arrays of ground conductors in electrical communication with ground plates.

Abstract translation: 一种集成电路组件，其包括堆叠的印刷陶瓷衬底层，并且包括围绕电导体迹线延伸的屏蔽外壳以及形成组装电路的互连。 屏蔽外壳被配置为减少电场和/或磁场泄漏或与迹线和互连的干扰。 该外壳在组装电路周围作为笼子提供，并且形成为与接地板电连通的接地导体阵列。

公开(公告)号：EP2454781A1

公开(公告)日：2012-05-23

申请号：EP09847410.9

申请日：2009-07-14

Applicant: Saab AB

Inventor： VICKES, Hans-Olof ,  KRISTIANSSON, Simon

IPC: H01P1/203 ,  H05K1/16

CPC classification number: H05K1/0251 ,  H01P1/20372 ,  H01P5/028 ,  H05K1/0222 ,  H05K1/0227 ,  H05K1/0239 ,  H05K2201/09609 ,  H05K2201/0979

Abstract: The invention refers to a filter unit (1) and a corresponding printed circuit board (2). The filter unit (1) and the printed circuit board (2) have been equipped with modified end portions (7, 8, 22, 23) being matched such that a number of filter units (1) can be used on the printed circuit board (2) without changing the printed circuit board (2).

公开(公告)号：EP1621054B1

公开(公告)日：2011-09-14

申请号：EP04728728.9

申请日：2004-04-21

Applicant: JonDeTech AB

Inventor： MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

IPC: H05K3/18

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

公开(公告)号：EP2031692A1

公开(公告)日：2009-03-04

申请号：EP08169722.9

申请日：2007-03-13

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Nair, Deepukumar M. ,  Walsh, Matthew R.

IPC: H01P1/203

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG)devices (10, 30), and a method for making and tuning tuned EBG devices (10, 30) are provided. The method includes the steps of providing first and second overlapping substrates (32, 32a), placing magnetically alignable conductive material (36) between the substrates (32, 32a), and applying a magnetic field (44, 45) in the vicinity of the magnetically alignable conductive material (36) to align at least some of the material into conductive vias (46, 47). The method further includes the steps of physically altering via characteristics of EBG devices (10, 30) to tune the bandpass and resonant frequencies of the EBG devices (10, 30).

公开(公告)号：EP1561368B1

公开(公告)日：2007-10-10

申请号：EP03783214.4

申请日：2003-11-07

Applicant: PPG Industries Ohio, Inc.

Inventor： OLSON, Kevin, C. ,  WANG, Alan, E.

IPC: H05K3/44 ,  H01L21/48

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

公开(公告)号：EP1631130A2

公开(公告)日：2006-03-01

申请号：EP05018486.0

申请日：2005-08-25

Applicant: HIROSE ELECTRIC CO., LTD.

Inventor： Matsuo, Tsutomu, Hirose Electric Co., Ltd

IPC: H05K1/02 ,  H01L23/528

CPC classification number: H05K1/116 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/10189 ,  H01L2924/00

Abstract: In a transmission circuit board, ground terminal portions (10) are disposed at every other two rows in both end columns. Each of signal circuit layers (20) includes at least a pair of adjacent signal connecting portions electrically connected to a pair of the wiring portions (21, 22) arranged in parallel in a row direction and the column direction different from those on an adjacent signal circuit layer. Each of the ground layers is electrically connected to at least one of the ground terminal portions (10) in the both end columns.

Abstract translation: 在传输电路板中，接地端子部分（10）在两个端部列中每隔两列设置。 每个信号电路层（20）至少包括一对相邻的信号连接部分，其电连接到沿着行方向并行布置的一对布线部分（21,22），并且列方向与相邻信号上的列方向不同 电路层。 每个接地层电连接到两端列中的至少一个接地端子部分（10）。

公开(公告)号：EP0988576A2

公开(公告)日：2000-03-29

申请号：EP98931120.4

申请日：1998-06-12

Applicant: Zetfolie B.V.

Inventor： RUITER, Jacobus, Christiaan, Gerardus, Maria ,  TERLOUW, Erik, Maarten ,  HADZIIOANNOU, Georges ,  BROUWER, Hendrik-Jan

IPC: G02F1/136 ,  H05K3/40 ,  H01B1/20

CPC classification number: H05K3/4038 ,  G02F1/1333 ,  G02F1/1345 ,  G02F1/135 ,  G02F1/1362 ,  H01B1/22 ,  H05K1/0287 ,  H05K3/105 ,  H05K2201/09609 ,  H05K2203/105

Abstract: Substrate (7; 7'; 10) and devices including such a substrate, the substrate having a first surface and a second surface extending substantially in parallel to the first surface, the substrate being of a material of a first conductivity and provided with a plurality of electrically conducting channels (21) which are extending exclusively in a direction perpendicular to the first and second surfaces, said channels having a second conductivity substantially larger than the first conductivity, the substrate being provided with at least one electrode (42) on either one of the first and second surfaces, contacting at least one of said channels, the at least one electrode (42) having a predetermined minimum dimension (D) in a contact area (A) with the substrate, and mutual distances between adjacent ones of the plurality of channels (21) being smaller than said minimum dimension of said at least one electrode (42).

公开(公告)号：EP0620702B1

公开(公告)日：1999-01-20

申请号：EP94810179.5

申请日：1994-03-23

Applicant: DYCONEX PATENTE AG

Inventor： Schmidt, Walter ,  Martinelli, Marco

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4038 ,  H05K1/0287 ,  H05K3/0041 ,  H05K3/06 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/068 ,  H05K2203/1476

公开(公告)号：EP0619935A1

公开(公告)日：1994-10-19

申请号：EP93902885.0

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： DISTEFANO, Thomas, H. ,  KHANDROS, Igor ,  GRUBE, Gary, W. ,  EHRENBERG, Scott, G.

IPC: H05K1 ,  H01L21 ,  H01L23 ,  H05K3

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

Abstract: L'invention concerne un ensemble de panneaux de circuit multicouche formé par stratification de panneaux de circuit (10) avec des couches intercalaire (12) contenant un matériau conductible coulant (48) dans les zones d'interconnexion et un matériau diélectrique coulant (30, 38) dans les autres zones. L'excès de matériau est capté dans des réservoirs (20) situés dans les panneaux du circuit. Lesdits matériaux coulants et les réservoirs permettent aux couches intercalaires de se comprimer et de compenser les tolérances des composants. Les panneaux superposés peuvent être pourvus de contacts (538) à leurs surfaces supérieures grâce à des conducteurs (527) s'étendant de la surface inférieure à la surface supérieure et des bornes (530) connectées à l'éxtrémité inférieure de chaque conducteur traversant. Les bornes et les contacts sont connectés les uns aux autres de manière non sélective au niveau de chaque interface de façon qu'à chaque fois qu'une borne et un contact sur des panneaux adjacents sont alignés l'un par rapport à l'autre, ils soient connectés l'un à l'autre. Cela permet de former des conducteurs composites verticaux s'étendant à travers une pluralité de panneaux. Le traitement sélectif des surfaces supérieures et inférieures des panneaux permet d'obtenir de manière sélective des interruptions dans les conducteurs verticaux.