公开(公告)号：US20100038117A1

公开(公告)日：2010-02-18

申请号：US12507551

申请日：2009-07-22

Applicant: Yechung CHUNG ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

Inventor： Yechung CHUNG ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/114 ,  H05K1/189 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.

Abstract translation: 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔， 所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块 半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。 示例性实施例涉及包括带布线基板的封装。

公开(公告)号：US07656044B2

公开(公告)日：2010-02-02

申请号：US12174273

申请日：2008-07-16

Applicant: Yoshiharu Ogata

Inventor： Yoshiharu Ogata

IPC: H01L23/52

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。

公开(公告)号：US07647447B2

公开(公告)日：2010-01-12

申请号：US10496920

申请日：2002-11-21

Applicant: Hua Li ,  Yuan Fuat Chin

Inventor： Hua Li ,  Yuan Fuat Chin

IPC: G06F13/00 ,  G11C5/02 ,  G06F17/50

CPC classification number: H05K1/181 ,  H05K2201/09236 ,  H05K2201/09772 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A data bus of a DVD+RW recorder between a DSP and a SDRAM usually needs a multilayer wiring board. In order to simplify the layout of the wiring board of the data bus there is provided a method for connecting at least a first and a second integrated circuit by providing the first integrated circuit having a plurality of first logical I/O ports physically arranged in a first order at the periphery, and providing the second integrated circuit having a plurality of second logical I/O ports physically arranged in a second order at the periphery, wherein each first I/O port is to be connected to one of said second I/O ports. The first and second I/O logical ports are connected independently from the first and/or second physical order, so that connection lines do not cross each other.

Abstract translation: DSP与SDRAM之间的DVD + RW刻录机的数据总线通常需要多层布线板。 为了简化数据总线的布线板的布局，提供了一种通过提供第一集成电路来连接至少第一和第二集成电路的方法，该第一集成电路具有物理地布置在第一和第二集成电路中的多个第一逻辑I / O端口 并且提供第二集成电路，该第二集成电路具有多个第二逻辑I / O端口，该第二逻辑I / O端口在外围以二级物理地布置，其中每个第一I / O端口将被连接到所述第二I / O端口 第一和第二I / O逻辑端口独立于第一和/或第二物理顺序连接，使得连接线不互相交叉。

公开(公告)号：US07439614B2

公开(公告)日：2008-10-21

申请号：US11139238

申请日：2005-05-26

Applicant: Yasunori Inoue ,  Ryosuke Usul ,  Yasuhiro Kohara ,  Nobuhisa Takakusaki ,  Takeshi Nakamura

Inventor： Yasunori Inoue ,  Ryosuke Usul ,  Yasuhiro Kohara ,  Nobuhisa Takakusaki ,  Takeshi Nakamura

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/34

CPC classification number: H01L23/3735 ,  H01L21/4857 ,  H01L21/4871 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.

Abstract translation: 在根据本发明的混合集成电路装置10的制造方法中，在第一布线层18A上设置第一虚设图案D 1。此外，第二布线层18B设置第二虚设图案D 2 第一虚设图案D 1和第二虚设图案D 2通过贯穿绝缘层17的连接部25连接。 因此，可以主动地执行通过虚拟图案的散热。 此外，即使在形成多层布线的情况下，也可以提供能够确保散热性的电路装置。

公开(公告)号：US20080236879A1

公开(公告)日：2008-10-02

申请号：US12058040

申请日：2008-03-28

Applicant: Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

Inventor： Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/383 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/056 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/09727 ,  H05K2201/09772 ,  H05K2201/0989 ,  H05K2203/0307 ,  H05K2203/0361 ,  H05K2203/049 ,  H05K2203/0542 ,  H05K2203/0723 ,  H05K2203/1152 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Provided are a circuit board with enhanced moisture resist and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. A circuit board of the present invention includes: a substrate; wirings formed on the main surface of the substrate; a cover layer covering the wirings excluding the regions to be connectors; back electrodes formed on the bottom surface of the substrate; and through-hole electrodes formed so as to penetrate the substrate, and thereby connecting the wirings and the back electrodes. On surfaces of each of the wirings in this circuit board, convex portions on the periphery of the substrate are set larger in width than convex portions in a center portion of the substrate. With this configuration, adhesion reliability between the wirings and the cover layer under a thermal cycle load can be enhanced.

Abstract translation: 提供了一种具有增强的抗湿性的电路板和制造该电路板的方法，以及电路装置和该电路装置的制造方法。 本发明的电路板包括：基板; 在基板的主表面上形成的布线; 覆盖除了作为连接器的区域的布线的覆盖层; 形成在基板的底面上的背面电极; 以及形成为穿透基板的通孔电极，从而连接布线和背面电极。 在该电路基板的各配线的表面上，基板周边的凸部的宽度比基板的中央部的凸部的宽度大。 利用这种结构，可以提高热循环负载下的布线与覆盖层之间的粘附可靠性。

公开(公告)号：US20080223608A1

公开(公告)日：2008-09-18

申请号：US12046893

申请日：2008-03-12

Applicant: Takao NISHIMURA

Inventor： Takao NISHIMURA

IPC: H05K1/18

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/15798 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09272 ,  H05K2201/09381 ,  H05K2201/09709 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate includes a plurality of electrode terminals, to which external connection terminals of an electronic component are coupled, arranged in a row on one principal surface thereof, wherein the electrode terminals each include: a first linear portion; a second linear portion extending from an end of the first linear portion in a direction different from a direction of the first linear portion; and a bent portion that is a part where the first linear portion and the second linear portion are connected.

Abstract translation: 布线基板包括多个电极端子，电子部件的外部连接端子与该电极端子的一个主表面上排成一行，电极端子各自包括：第一直线部分; 第二直线部分，沿与第一直线部分的方向不同的方向从第一直线部分的端部延伸; 以及作为第一直线部和第二直线部连接的部分的弯曲部。

公开(公告)号：US20080042300A1

公开(公告)日：2008-02-21

申请号：US11708027

申请日：2007-02-20

Applicant: Takao Nishimura ,  Kazuyuki Aiba

Inventor： Takao Nishimura ,  Kazuyuki Aiba

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75743 ,  H01L2224/83096 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/83855 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/28 ,  H05K3/305 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/00012 ,  H01L2924/3512

Abstract: A circuit substrate for improving the reliability and productivity of a semiconductor device, and that semiconductor device. In a circuit substrate to which a semiconductor element is to be flip-chip mounted, at least one island-shaped electrically conductive layer is selectively disposed together with a wiring layer at an element mounting area where the semiconductor element is to be mounted, and an insulating resin layer is disposed over the island-shaped electrically conductive layer. The semiconductor element is secured at the element mounting area to the circuit substrate by an adhesion material to make a semiconductor device. With this, delaminating of the wiring layer inside the semiconductor device is suppressed, and the damage of an electrode is suppressed. The circuit substrate has high reliability and the semiconductor device, having the circuit substrate, is implemented.

Abstract translation: 一种用于提高半导体器件的可靠性和生产率的电路基板，以及该半导体器件。 在半导体元件将要倒装芯片安装的电路基板中，至少一个岛状导电层与要安装半导体元件的元件安装区域的布线层一起选择性地布置，并且 绝缘树脂层设置在岛状导电层上。 半导体元件通过粘合材料固定在元件安装区域到电路基板以制造半导体器件。 由此，能够抑制半导体装置内的布线层的分层，抑制电极的损伤。 电路基板具有高可靠性，并且实现了具有电路基板的半导体器件。

公开(公告)号：US07279771B2

公开(公告)日：2007-10-09

申请号：US11090029

申请日：2005-03-28

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

IPC: H01L29/00 ,  H05K1/14 ,  H05K1/03

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract translation: 在电容器安装的布线板中，以所需形状图案化的多个布线层被叠置在其间插入绝缘层，并且通过形成为在厚度方向上刺穿绝缘层的导体彼此连接。 去耦电容器电连接到用作布线层附近的电源线或接地线的布线层，并且安装成使得当电流通过电容器时，电流的方向被反转到 流过相关布线层的电流。

公开(公告)号：US20070164445A1

公开(公告)日：2007-07-19

申请号：US11650459

申请日：2007-01-08

Applicant: Daisuke Ejima

Inventor： Daisuke Ejima

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/13 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09772 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Aiming at adjusting the height of bump electrodes connected to lands on a substrate, a semiconductor device 100 has a first interconnect substrate 103 and a second interconnect substrate 101. On one surface of these substrates, first lands 111 and second lands 113 are provided. The plane geometry of the second lands 113 is a polygon characterized by the inscribed circle thereof having an area smaller than the area of the inscribed circle of the first land.

Abstract translation: 为了调整连接到衬底上的焊盘的凸起电极的高度，半导体器件100具有第一互连衬底103和第二互连衬底101。 在这些基板的一个表面上，设置有第一焊盘111和第二焊盘113。 第二平台113的平面几何形状是其内接圆的面积小于第一平台的内切圆的面积的多边形。

公开(公告)号：US20070109709A1

公开(公告)日：2007-05-17

申请号：US10582758

申请日：2004-12-22

Applicant: David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

Inventor： David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

IPC: H02H9/06

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

Abstract translation: 包括第一电极（120），第二电极（80）和屏蔽结构（70,110,150）的能量调节器结构在电路中提供改进的能量调节。 结构可以作为分立组件或集成电路的一部分存在。 能量调节器结构中的屏蔽结构不电连接到任何电路元件。