-
公开(公告)号：JPH0896569A
公开(公告)日：1996-04-12
申请号：JP5038495
申请日：1995-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO , GOLLA CARLA MARIA
Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.
-
公开(公告)号：JPH0883500A
公开(公告)日：1996-03-26
申请号：JP14503495
申请日：1995-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , CAMERLENGHI EMILIO
Abstract: PURPOSE: To obtain a memory device endurable in a gain reduction. CONSTITUTION: Column and/or row address decode means RDEC, CDEC comprise at least one address mapping nonvolatile memory NVM. A read and write control logic part CL comprises identifying means TST designed so as to identify a cell fail in a column and/or a row of a matrix MAT of a memory device; and means WM for writing an address corresponding to a column and/or a row RID existing in the matrix MAT on the nonvolatile memory NVM during normal operations, and cell characteristics can readily and effectively be decided.
-
公开(公告)号：JPH0883494A
公开(公告)日：1996-03-26
申请号：JP5377795
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.
-
公开(公告)号：JPH0870078A
公开(公告)日：1996-03-12
申请号：JP19746495
申请日：1995-08-02
Applicant: ST MICROELECTRONICS SRL
Inventor： POINELLI RENATO , MAZZOLA MAURO , CASATI PAOLO
IPC: H01L23/28 , H01L23/433 , H01L23/495 , H01L23/50
Abstract: PROBLEM TO BE SOLVED: To obtain a leadframe for supporting semiconductor device, where a heat radiator and a semiconductor chip attached to it are incorporated. SOLUTION: Two metal bars 3 mounted on a heat radiator 2 by conductive means 4 are provided, and the metal bar 3 is provided with a metallized area 5 which is designed for the welding of a thin gold wire to the electric terminal of a semiconductor chip and is set lower with respect to the top surface of the metal bar 3.
-
公开(公告)号：JPH0856148A
公开(公告)日：1996-02-27
申请号：JP11264895
申请日：1995-04-14
Applicant: ST MICROELECTRONICS SRL
Inventor： MENNITI PIETRO , NOVELLI ALDO
IPC: H03K19/0185
Abstract: PURPOSE: To obtain a voltage shift circuit operable with high voltage by supplying a grounded correlation signal for an output encoding the same information as a high voltage correlation signal by an input. CONSTITUTION: The level shift circuit 1 of voltage input signals S and SN show at least first and second high voltage levels and the circuit is composed of two branches, each of which consists of current modulators 6, 7, 9, 14, 15, 17 and signal converters 8 and 16. A current modulator is supplied with two signals of mutually opposite phases to generate current signals I7 and I15 being values depending on the level of each input signal and a signal converter converts a current signal to ground related voltage signals V1 and V2. The signal converter forms a signal terminating differential circuit 20 and the output 21 of the circuit 20 shows a low voltage digital signal which can be generated by a normal digital circuit and receives no influence by a noise or the fluctuation of supply voltage.
-
Patent Agency Ranking
公开(公告)号：JPH0856147A
公开(公告)日：1996-02-27
申请号：JP9682795
申请日：1995-04-21
Applicant: ST MICROELECTRONICS SRL
Inventor： PENZA LUIGI , TIMINERI CALOGERO
IPC: H03K17/16 , H03K17/687 , H03K17/695 , H03K19/003 , H03K19/0175
Abstract: PURPOSE: To obtain an output buffer current slew rate control integrated circuit receiving no influence from conventional kinds of restrictions. CONSTITUTION: The output buffer current slew rate control integrated circuit provided with a first MOS type transistor means 1 supplying a current IOUT for load impedance ZL is provided with current generating means BIAS1, BIAS2 and C1 to C4 generating constant currents ID1 and IC1 and operates these constant currents in switching the input signal IN of the output buffer 1 between two logical states. Thereby, first transistor means P1 and N1 are driven by driving voltages V2 and V3 with a slew rate decided by the constant currents ID1 and IC1 by driving the control input terminals 2 and 3 of the first transistor means P1 and N1.
-
公开(公告)号：JPH0847246A
公开(公告)日：1996-02-16
申请号：JP1306395
申请日：1995-01-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , PADOAN SILVIA
Abstract: PURPOSE: To supply large power in the case that an input/output voltage ratio is low or a power supply voltage is low by mutually connecting in parallel pull-up stages between a reference potential line and an output line. CONSTITUTION: This charge pump circuit 1 is provided with numerous stages 21 -2n connected in parallel to each other between the reference potential line 3 and the output line 4, the respective stages 21 -2n are provided with bootstrap capacitors 51 -5n , the one side is connected to nodes 71 -7n and the other terminals are connected to nodes 61 -6n . Then, when inverters 121 -12n are switched, the odd-numbered stages 21 , 23 ,... are switched to a charge transfer mode, the even- numbered stages are switched to a charging mode. When a switching edge reaches a stage 2n-1 which is one next to the last, an AND circuit 15 and a NOR circuit 16 are switched, shifting along the inverters 121 -12n is performed, the odd-numbered stages 21 , 23 ,... are charged, and the even-numbered stages 22 , 24 ,... transfer the stored charges. As a result, even in the case that an input voltage ratio is low, voltage is efficiently boosted and a large power is supplied.
-
公开(公告)号：JPH0846462A
公开(公告)日：1996-02-16
申请号：JP8842795
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: PURPOSE: To provide a low-frequency amplifier for eliminating negative peak in an output voltage that is easily and widely adaptable. CONSTITUTION: In the low-frequency amplifier 30 which is equipped serially with an input step 2, a voltage amplifier step 3 and an output step 4, other input step 31 is provided to be turned on during a transient term only for preventing a negative voltage peak from being generated by an output terminal 19 during a transient term from the disabled operation condition to the operation condition and thereby a capacitor 18 in the voltage amplifier is charged up to the specified electric charge value.
-
149.发明专利
公开(公告)号：JPH0846456A
公开(公告)日：1996-02-16
申请号：JP16656895
申请日：1995-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： REZZI FRANCESCO , BASCHIROTTO ANDREA , CASTELLO RINALDO
IPC: H03F3/45
Abstract: PURPOSE: To highly reduce common mode current signals in an output terminal. CONSTITUTION: The method for canceling common mode current signals at the second transconductor circuit C2 output terminals OP1 and OM1, which are provided with the same differential mode transconductance value as the second common mode conductance value is provided with a first transconductor circuit C1, and a second transconductor circuit C2. The circuit C1 is provided with the same differential mode transconductance value as the first common mode transconductance value. The circuit C2 is provided with the common mode transconductance whose coefficient is almost the same as the second value and whose code is opposite in parallel to the first transconductor circuit C1.
-
公开(公告)号：JPH0845289A
公开(公告)日：1996-02-16
申请号：JP5377695
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To set a timing accurately while suppressing noise by loading a simulate signal to an output simulation circuit through a switch subjected to required control and resetting a simulate generation circuit in response to the variation of simulate signal. CONSTITUTION: Upon provision of a sync signal SYNC, a simulate signal SP is generated from the simulate signal generator 34 of delay FF and a load block signal SS makes a transition to L through a switch 35 opened by a load enable signal L before being loaded to an unblocked output simulation circuit 21. When the signal SP is inverted to 'L', output is inverted to H through a NAND gate 30 and an inverter 32 and the generator 34 is reset instantaneously through a monostable multivibrator 33. On the other hand, a signal SS is inverted to H and loading to the circuit 21 is blocked. According to the circuitry, loading of signal and blocking of loading are controlled accurately and the effect of noise due to housing is suppressed.
-
-
-
-
-
-
-
-
-
Search Results
5324
records
(took 0.056 seconds)
