公开(公告)号：EP0436848A3

公开(公告)日：1991-10-09

申请号：EP90123638.0

申请日：1990-12-08

Applicant: International Business Machines Corporation

Inventor： Chance, Dudley Augustus

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/66

CPC classification number: H01L23/66 ,  H01L23/5384 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0289 ,  H05K1/115 ,  H05K2201/09609 ,  H05K2201/09681 ,  H05K2201/09718 ,  H01L2924/00

Abstract: Electrical impedance matching for through plane connections or vias (20-44) in a multiplane laminated wiring structure is provided by arranging the vias in patterns conforming to a standard characteristic impedance configuration. The pattern may be a five wire configuration with four vias surrounding the fifth and repeated over the area of the plane.

公开(公告)号：EP0148506B1

公开(公告)日：1988-11-02

申请号：EP84116410.6

申请日：1984-12-27

Applicant: HITACHI, LTD.

Inventor： Tanaka, Minoru ,  Hirota, Kazuo ,  Murata, Akira ,  Kobayashi, Fumiuki ,  Takenaka, Takaji

IPC: H01C13/02 ,  H01C1/142 ,  H01L25/16

CPC classification number: H01C13/02 ,  H01C1/142 ,  H05K1/116 ,  H05K1/167 ,  H05K3/388 ,  H05K3/42 ,  H05K2201/0317 ,  H05K2201/09609 ,  H05K2203/0361

公开(公告)号：EP0154909A3

公开(公告)日：1986-07-16

申请号：EP85102330

申请日：1985-03-01

Applicant: HOECHST AKTIENGESELLSCHAFT

Inventor： Seibel, Markus, Dr. Dipl.-Chem.

IPC: H05K03/42

CPC classification number: B05D5/12 ,  H05K1/0287 ,  H05K1/05 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/108 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394

Abstract: Es wird ein Verfahren zur Herstellung von durchkontak tierten elektrischen Leiterplatten beschrieben, bei dem eine Platte aus Isolierstoffmaterial mit in rasterartigem Muster angeordneten Durchkontaktierungslöchern versehen wird, deren Wandungen mit einer Metallschicht überzogen wer den und die auf mindestens einer Seite mit einer leitfähigen Metallschicht bedeckt wird. Die Metallschicht wird nach dem Metallisieren der Löcher bildmässig abgedeckt, und die nicht abgedeckten Bereiche der Metallschicht werden entweder durch Metallablagerung verstärkt oder durch Ät zen entfernt. Zugleich mit der Metallschicht wird ein Teil der Löcher in der Weise abgedeckt, dass im fertigen Pro dukt nur der gewünschte Anteil aller Löcher als Leitkontakt wirksam wird. Das Verfahren erlaubt die Fertigung von vor gebohrtem bzw. vorgelochtem und vormetallisiertem Ba sismaterial für gedruckte Schaltungen in Grosserie.

Abstract translation: 描述了一种用于制造通孔电镀印刷电路板的方法，其中绝缘材料的基板设置有以栅格图案布置的电镀通孔，并且其壁被涂覆有导电 金属层。 该板在其至少一侧覆盖有导电金属层。 在金属化孔之后，金属层被成像地覆盖，未被覆盖的金属层的区域通过金属沉积或通过蚀刻去除而增强。 与金属层一起，部分孔被覆盖，使得只有所有孔的所需部分用作最终产品中的导电连接。 本发明的方法允许大规模制造用于印刷电路的预钻孔或预先预先金属化的基底材料。

公开(公告)号：EP0130430A3

公开(公告)日：1986-04-30

申请号：EP84106836

申请日：1984-06-15

Applicant: International Business Machines Corporation

Inventor： Willie, Goff, Jr.

IPC: H05K03/46 ,  H05K03/08

CPC classification number: H05K3/08 ,  H05K1/09 ,  H05K3/325 ,  H05K3/368 ,  H05K2201/0323 ,  H05K2201/09609 ,  H05K2201/10378 ,  Y10T29/49004 ,  Y10T29/49126

Abstract: By use of an electroerosion technique a plurality of conductive lines are isolated out of an electrically conductive layer supported on an isolating substrate of a sheet (1) having holes in a distinct pattern. Several sheets (1) are superimposed in different planes and are alternately mixed with inerplane spacer-connector layers (24) between a terminal block (32) and a pressing guide block (33). The interplane spacer-connector layer (24) contains connectors (26) with contact areas (27, 28) interconnected with each other and make contact with isolated zones in different superimposed planes of sheets (1). The terminal block (32) is provided with sockets (35) for holding the terminals of circuit components of the to-be-developed electrical circuit.

公开(公告)号：EP0148506A3

公开(公告)日：1986-04-09

申请号：EP84116410

申请日：1984-12-27

Applicant: HITACHI, LTD.

Inventor： Tanaka, Minoru ,  Hirota, Kazuo ,  Murata, Akira ,  Kobayashi, Fumiuki ,  Takenaka, Takaji

IPC: H01C13/02 ,  H01C01/142 ,  H01L25/16

CPC classification number: H01C13/02 ,  H01C1/142 ,  H05K1/116 ,  H05K1/167 ,  H05K3/388 ,  H05K3/42 ,  H05K2201/0317 ,  H05K2201/09609 ,  H05K2203/0361

Abstract: Resistors (4; 4a, 4b) are formed on one surface of a board (1; 1a, 1b, 1c) having through hole conductors (2; 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2h', 7aa) arranged like a lattice, an electrode (6) is further formed on the surface of these resistors, and the electrodes over the through hole conductors are coaxially removed, thereby forming substantially disk-like resistors (4a, 4b).

公开(公告)号：EP0145549A2

公开(公告)日：1985-06-19

申请号：EP84402266.5

申请日：1984-11-09

Applicant: THOMSON-CSF

Inventor： Brault, Roland

IPC: H05K1/00

CPC classification number: H05K1/112 ,  H05K1/0295 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09954 ,  H05K2201/10689

Abstract: La carte imprimée à empreintes conforme à la présente invention est munie de plusieurs rangées (70 à 79, 80, 81) de trous conducteurs espacés d'un multiple d'un pas constant et disposées selon un motif répétitif, chaque trou conducteur étant relié à une pastille de câblage prévue sur la face câblage à l'intérieur du motif. D'autre part les trous de certaines rangées (70, 71, 76, 77, 78, 79) contigües sont connectés à des pistes de câblage (12) prévues sur la face composants (5) de la carte et les trous d'autres rangées contigües (72, 73, 74, 75) sont connectés ensemble et reliés à la même pastille de câblage.
Cette carte est utilisée principalement pour la réalisation de circuits imprimés au stade de maquette ou prototype.

公开(公告)号：EP2801123A1

公开(公告)日：2014-11-12

申请号：EP12864500.9

申请日：2012-11-01

Applicant: Cray Inc.

Inventor： KIM, Hyunjun ,  CONGER, Jeffrey Scott ,  SCOTT, Gregory Erwin

IPC: H01P1/00

CPC classification number: H05K1/0225 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.

公开(公告)号：EP2174535A1

公开(公告)日：2010-04-14

申请号：EP07871188.4

申请日：2007-10-19

Applicant: Second Sight Medical Products, Inc.

Inventor： OK, Jerry ,  GREENBERG, Robert, J.

IPC: H05K3/40

CPC classification number: H05K3/4061 ,  B32B37/14 ,  C04B35/10 ,  C04B37/00 ,  C04B2237/064 ,  H05K1/0306 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/005 ,  H05K3/12 ,  H05K3/1225 ,  H05K3/1233 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4629 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2203/1147 ,  H05K2203/308 ,  Y10T156/10

Abstract: A method for fabricating the hermetic electrical feedthrough. The method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thickfilm paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.

Abstract translation: 一种用于制造密封电馈通的方法。 该方法包括提供具有上表面和下表面的陶瓷片，在从所述上表面延伸到所述下表面的所述陶瓷片中形成至少一个通孔，将导电厚膜糊剂插入所述通孔中，将陶瓷片层压 在上陶瓷片和下陶瓷片之间通过孔填充糊状物以形成层压陶瓷基板，将层叠的陶瓷基板烧制至烧结层叠陶瓷基板的温度，并使填充有通孔的浆料形成金属化通孔， 层叠陶瓷基板，以形成围绕所述金属化通孔的气密密封，并从烧结的层叠陶瓷基板上除去上部陶瓷片和下部陶瓷片材，以露出金属化通孔的上表面和下表面。

公开(公告)号：EP2146557A1

公开(公告)日：2010-01-20

申请号：EP09164411.2

申请日：2009-07-02

Applicant: Thales Holdings UK Plc

Inventor： Lawson, Graham ,  Loiselet, Emmanuel

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09618 ,  H01L2924/00014

Abstract: An hermetically sealed integrated microwave circuit comprising a coplanar waveguide on a PCB (3, 4) electrically connected on one major surface to an IC, and thermally and electrically connected to a BGA (5) on its opposite major surface, in which the PCB has at least first and second printed layers, a microwave signal path extends from a ball of the BGA through a through-hole in both printed layers to the coplanar wave guide, and plural ground paths extend from balls (51) of the BGA (5) through first through-holes in the first printed layer of the PCB and through second through-holes of the second printed layer of the PCB, the first and second through-holes being non-coincident, to allow for an hermetic seal across the PCB whilst introducing a predetermined impedance in the PCB between the signal and ground paths.

Abstract translation: 一种密封的集成微波电路，包括在一个主表面上电连接到IC上的PCB（3,4）上的共面波导，并且热电连接到其相对的主表面上的BGA（5），其中PCB具有 至少第一和第二印刷层，微波信号路径从BGA的球通过两个印刷层中的通孔延伸到共面波导，并且多个接地路径从BGA（5）的球（51）延伸， 通过PCB的第一印刷层中的第一通孔和PCB的第二印刷层的第二通孔，第一和第二通孔不重合，以允许穿过PCB的气密密封，同时 在信号和接地路径之间的PCB中引入预定的阻抗。

公开(公告)号：EP1615485A4

公开(公告)日：2009-04-22

申请号：EP04726017

申请日：2004-04-06

Applicant: IBIDEN CO LTD

Inventor： KATO SHINOBU

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K3/42

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599

Abstract: In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

Abstract translation: 用于供电的接地孔和通孔（36P）的通孔（36E）以格子形式布置在核心板（30）上，从而抵消在X方向和Y方向上感生的电动势。 从而降低互感，并且即使安装高频IC芯片也能防止误操作和错误。 因此，可以提高电特性和可靠性。