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公开(公告)号:JPH0773140A
公开(公告)日:1995-03-17
申请号:JP5280994
申请日:1994-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor: ALINI ROBERTO , MOLONEY DAVID , GORNATI SILVANO , PORTALURI SALVATORE
Abstract: PURPOSE: To reduce the integration area and to accelerate the processing concerning a structure provided with a serial type interface for connection to a data transmission line, by connecting a part of a register to the bundled line and transmitting both a register address and data. CONSTITUTION: A decoded address latch 5 stores the output state of an address decoder 4 until the other address is transmitted through a multiplex bus 2. Only when this address is the address of a designated data register 1, according to the output of this latch 5, data transmitted after this address are written in this register. A write line 9 transmits a data write signal through a logic gate 7 of AND type. A data read circuit means 3 reads data out of this register 1 so as to repeat data from the multiplex bus 2. Only when the transmitted address is as prescribed, a read command starts reading from this register 1.
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公开(公告)号:JPH0772270A
公开(公告)日:1995-03-17
申请号:JP1033094
申请日:1994-02-01
Applicant: ST MICROELECTRONICS SRL , MARELLI AUTRONICA
Inventor: LOMBRESCHI GIAMPAOLO , BRAMBILLA MASSIMILIANO
Abstract: PURPOSE: To provide a circuit capable of generating control pulse trains in various operating conditions by using one specified bit counter for both of a normally operating condition and a one-operation time reset condition. CONSTITUTION: An input part receives three types of signals, a signal CLOCK, a signal RESET and a signal PULSE. The signal CLOCK is input to a frequency: division 4 to generate two frequency signals. A counter: 50M2 is provided with a counter 2A to generate a signal SX with the second frequency, which is a quick clock time reset pulse basic signal SX with high and low logic conditions. A multiplexer MUX 3 selectively sends both of a quick time reset signal SX and a slow time reset signal SN as the functions of a signal SECS to an output part S1 or S2 in a circuit. A counter: 11 bit 1 receives the signal PULSE, the signal RESET, the signal QSX and the first frequency signal to selectively control the reversion of a current in a clock motor.
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公开(公告)号:JPH0745730A
公开(公告)日:1995-02-14
申请号:JP2281894
申请日:1994-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor: PIO FEDERICO , RIVA CARLO
IPC: H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: PURPOSE: To increase the reliability and life of a storage circuit, while reducing the deterioration of a tunnel oxide. CONSTITUTION: A double-level polysilicon EEPROM memory cell with a control gate 15 that is connected in series with a selective transistor 14 and is located at the upper layer of a floating gate 12 and a dielectric layer 11 between the gates has a region 10, consisting of an n -type region 18 and an n -type region.
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公开(公告)号:JPH06350425A
公开(公告)日:1994-12-22
申请号:JP9588294
申请日:1994-04-09
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor: BONTEMPO GREGORIO , MILAZZO PATRIZIA , ALZATI ANGELO
IPC: H03K17/04 , H03K17/0412 , H03K17/16 , H03K17/687
Abstract: PURPOSE: To provide a control circuit substantially equalizing the delay of the turn-on and turn-off of an output signal by reducing the delay of switching. CONSTITUTION: The control circuit includes a first current oscillator I1 charging the driving node of a power transistor and a second current oscillator I2 discharging a driving node and is provided with a third current oscillator I3 for discharging a node. Discharge by the third current oscillator is controlled by a signal to adjust a turn-off delay time and a turn-on delay time.
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公开(公告)号:JPH06325592A
公开(公告)日:1994-11-25
申请号:JP5878794
申请日:1994-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor: OLIVO MARCO , PASCUCCI LUIGI
Abstract: PURPOSE: To unnecessitate a specified load circuit to program cells in a redundancy row by positioning at an intersection a line and a row of matrix itself and providing matrix consisting of memory cells. CONSTITUTION: A load circuit 3 for programming is connected to a common drain of transistors MS and MSR of each bucket 1. The circuit 3 consists of P channel MOS type transistor MP1, its drain is connected to the common drain of the transistors MS and MSR, its source is connected to programming voltage VP and its gate is connected to an input of a circuit 4 which has a NAND logic function. The circuit 4 is provided with a P channel MOS type load transistor M41, its source and drain are respectively connected to the voltage VP and a gate of the MP1 and make them ground electric potential. A drain of a transistor M42 is connected to a drain of the transistor M41, a drain of a transistor M43 is connected to its source, the source is ground electric potential and signals YMO to YM7 are given here. Thus, a signal DIN to program is acquired.
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公开(公告)号:JPH06303290A
公开(公告)日:1994-10-28
申请号:JP33163093
申请日:1993-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor: CONSIGLIO PIETRO , ANTONINI CARLO , VANALLI GIANPIETRO
Abstract: PURPOSE: To provide a device having a monolithically integrated line switch by providing a circuit interface which drives a pair of switches and providing the circuit interface with a unidirectional current pass circuit element which controls a driving current generated internally. CONSTITUTION: An input terminal E for application of an external electric signal related to a circuit node G and a circuit interface means CI which has output terminals to drive switches SW2 and SW3 through an actuator circuit ACT are provided. In the circuit interface CI, a unidirectional current circuit element like a diode D1 is connected in parallel with the switch SW3 between a terminal 36 of a bridge circuit PP and a circuit node G. That is, the switch SW3 can be operated by the diode D1 provided between the bridge circuit PP and a substrate. Consequently, the driving current generated in the circuit interface means CI by the external electric signal goes to the substrate through the diode in any polarity state.
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公开(公告)号:JPH06244930A
公开(公告)日:1994-09-02
申请号:JP18150993
申请日:1993-07-22
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , ERRATICO PIETRO
Abstract: PURPOSE: To synthesize impedance related with the circuit of a telephone subscriber connected with a pair-wire telephone line. CONSTITUTION: One precision resistor R is serially connected with a line 3, and this circuit is provided with at least one low-pass filter 8 and an amplifier 7 between the filter 8 and the resistor R. Thus, a terminal impedance can be synthesized with a balanced impedance by one outside precision element.
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公开(公告)号:JPH06236890A
公开(公告)日:1994-08-23
申请号:JP20718493
申请日:1993-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor: POLETTO VANNI , MORELLI MARCO
IPC: H01L29/73 , G05F1/569 , H01L21/331 , H03K17/0422
Abstract: PURPOSE: To provide a method for easily adjusting saturation, unrelated to the layout of a power transistor, unlike the known anti-saturation system, in which an actually generated substrate current is traced by the operation of the transistor in the saturation region, in place of tracing the generation of direct bias of collector/base junction for the power transistor as an index of saturation condition of the transistor. CONSTITUTION: A sensing resistor RS is connected in the path to limit a current IS, which is injected to a substrate from a saturation transistor T1 . A first signal, indicating saturation condition of the transistor, is detected and this signal is compared with a reference voltage VS. When the signal becomes higher than the threshold, a base current IB is reduced.
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公开(公告)号:JPH06224692A
公开(公告)日:1994-08-12
申请号:JP22898193
申请日:1993-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO
Abstract: PURPOSE: To integrate a capacitor in a circuit. CONSTITUTION: A circuit 1 is composed of a resistor Re connected in series with the first terminal L+ of a telephone line 3 and one set of current mirror circuits 4, 6, 8, and 10. The current mirror circuits 4, 6, 8, and 10 are connected to a first terminal in a closed loop and multiply the resistance value of the resistor Re by prescribed values when DC signals or signals having a very low frequency are inputted to a telephone subscriber's line 2.
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公开(公告)号:JPH06224689A
公开(公告)日:1994-08-12
申请号:JP18823293
申请日:1993-07-29
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO
Abstract: PURPOSE: To provide an inexpensive high-accuracy RC filter having structural and operational features suitable for integrated circuits requiring very large time constants. CONSTITUTION: An RC filter 1 is provided with a resistor R connected between the input Vin and output Vout of the filter and an amplifier 5 which is connected behind the resistor R and the output of which is fed back to its input through a capacitor. By using such a simple device, a filter having a large time constant while using small-sized components occupying small spaces in an integrated circuit can be manufactured by utilizing the already known mirror effect.
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