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    Memory support provided with elements of ferroelectric material and improved non-destructive reading method thereof
    174.
    发明公开
    Memory support provided with elements of ferroelectric material and improved non-destructive reading method thereof 审中-公开
    物理化学物质和化学物质和化学物质Leseverfahrendafür

    公开(公告)号：EP2482287A1

    公开(公告)日：2012-08-01

    申请号：EP12153546.2

    申请日：2012-02-01

    Applicant: STMicroelectronics Srl

    Inventor： Scalia, Antonio Maria ,  Greco, Maurizio

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: A method for non-destructive reading of an information datum stored in a memory (10) that includes a first word line (18a), a first bit lines and a second bit lines, and a first ferroelectric transistor (14), which is connected between the bit liness and has a control terminal (20c) coupled to the first word line, the method comprising the steps of: applying to the first word line (18a) a first reading electric quantity (Vread); generating a first difference of potential (Vsense) between the first and second bit liness (16a, 17a); generating a first output electric quantity (i TOT ; V a ); applying to the first word line (18a) a second reading electric quantity (V ref ); generating a second difference of potential (Vsense) between the first and second bit liness (16a, 17a); generating a second output electric quantity (i TOT ; V b ); comparing the first and second output electrical quantities (V a , V b ) with one another; and, on the basis of a result of said comparison, determining the logic value of the information datum.

    Abstract translation: 一种存储在存储器（10）中的信息数据的非破坏性读取方法，该存储器包括第一字线（18a），第一位线和第二位线以及连接的第一铁电晶体管（14） 在所述位置之间并具有耦合到所述第一字线的控制端子（20c），所述方法包括以下步骤：向所述第一字线（18a）施加第一读取电量（Vread）; 产生第一和第二位亮度（16a，17a）之间的第一电位差（Vsense）; 产生第一输出电量（i TOT; V a）; 向第一字线（18a）施加第二读数电量（V ref）; 产生所述第一和第二位亮度（16a，17a）之间的第二电位差（Vsense）; 产生第二输出电量（i TOT; V b）; 将第一和第二输出电量（V a，V b）彼此进行比较; 并且基于所述比较的结果，确定信息数据的逻辑值。

    Radiation hardened bipolar junction transistor
    177.
    发明公开
    Radiation hardened bipolar junction transistor 有权
    Strahlungsgeschützter双波导管

    公开(公告)号：EP2472572A1

    公开(公告)日：2012-07-04

    申请号：EP11196036.5

    申请日：2011-12-29

    Applicant: STMicroelectronics Srl ,  STMicroelectronics Asia Pacific Pte Ltd.

    Inventor： Patti, Alfonso ,  Schillaci, Antonino ,  Marrone, Bartolomeo ,  Grasso, Gianleonardo ,  Kumar, Rajesh

    IPC: H01L21/331 ,  H01L29/732 ,  H01L29/40

    CPC classification number: H01L29/402 ,  H01L29/66272 ,  H01L29/7322

    Abstract: A method is proposed for integrating a bipolar injunction transistor (100) in a die of semiconductor material having a main surface (105) covered by a sacrificial insulating layer (110), the die including a collector region (Rc) of a first type of conductivity extending from the main surface. The method includes the steps of forming an intrinsic base region (Rbi) of a second type of conductivity extending in the collector region from the main surface through an intrinsic base window (Wbi) of the sacrificial insulating layer, and forming an emitter region (Re) of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window (We) of the sacrificial insulating layer; in the solution according to an embodiment of the invention, the method further includes the steps of removing the sacrificial insulating layer, forming an intermediate insulating layer (115) on the main surface, the intermediate insulating layer having a thickness lower than a thickness of the sacrificial layer, and forming an extrinsic base region (Rbe) of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window (Wbe) of the intermediate insulating layer, the extrinsic base region having a concentration of impurities higher than a concentration of impurities of the intrinsic base region and being separated from the emitter region by a portion of the intrinsic base region.

    Abstract translation: 提出了一种用于将双极性抑制晶体管（100）集成在具有由牺牲绝缘层（110）覆盖的主表面（105）的半导体材料的管芯中的模具，该管芯包括第一类型的集电极区域（Rc） 电导率从主表面延伸。 该方法包括以下步骤：通过牺牲绝缘层的本征基本窗口（Wbi）从主表面形成在集电极区域中延伸的第二类型导电的本征基极区域（Rbi），并形成发射极区域 ），所述第一类型导电体在所述本征基极区域中从所述主表面延伸穿过所述牺牲绝缘层的发射极窗口（We）; 在根据本发明的实施例的方案中，该方法还包括以下步骤：去除牺牲绝缘层，在主表面上形成中间绝缘层（115），中间绝缘层的厚度低于 牺牲层，并且通过中间绝缘层的非本征基窗（Wbe）从主表面形成在本征基区中延伸的第二类导电的非本征基区（Rbe），所述非本征基区具有 杂质高于本征碱性区域的杂质浓度，并通过本征碱性区域的一部分与发射极区域分离。

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