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公开(公告)号：KR100531012B1
公开(公告)日：2005-11-28
申请号：KR1020030050042
申请日：2003-07-22
Applicant: 한국전자통신연구원
IPC: H01L21/22
Abstract: 본 발명은 반도체 소자의 제조 공정에서 열산화, 열확산, 각종 어닐과 같은 웨이퍼 프로세스에 사용되는 횡형 확산로에 관한 것이다. 원통 형태의 석영 튜브에는 비스듬히 절재된 모양의 경사진 개구부가 형성되어 보트가 내부에 위치된 상태에서 개구부를 통해 웨이퍼를 보트에 용이하게 적재할 수 있으며, 개구부를 밀폐하기 위한 튜브 덮개에는 다수의 가스 유출공을 갖는 가스 주입구가 형성되어 반응가스가 석영 튜브 내부로 균일하게 공급됨으로써 두께가 균일한 박막을 성장시킬 수 있다. 또한, 본 발명에 따르면 튜브 덮개가 개구부에 덮힌 상태에서 석영 튜브가 반응실로 이동하기 때문에 외부로부터 대기가스의 유입이 차단되어 자연산화막의 성장이 최소화된다.
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公开(公告)号：KR1020050065888A
公开(公告)日：2005-06-30
申请号：KR1020030097048
申请日：2003-12-26
Applicant: 한국전자통신연구원
IPC: H01L31/10
CPC classification number: H01L31/02161 , H01L31/02019 , H01L31/022408
Abstract: 본 발명은 반도체 위에 계면전하 또는 포획전하를 가지는 투광성의 비전도성 물질을 증착하여, 반도체 표면을 공핍시키고, 이 공핍영역을 빛의 감지영역으로 사용하는 광센서를 제작함으로서, 자외선 및 푸른색 영역 파장의 빛에 대한 감지 능력을 향상시키고, 가시광 및 적외선 영역의 광을 여과할 수 있으며, 일반적인 실리콘 CMOS 공정과도 양립할수 있는 광센서를 제작하는 것이다.
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公开(公告)号：KR100485129B1
公开(公告)日：2005-04-25
申请号：KR1020020070288
申请日：2002-11-13
Applicant: 한국전자통신연구원
IPC: H01J1/30
Abstract: 본 발명은 전계 방출 소자의 제조 방법에 관한 것으로, 케소드를 형성하기 위해 도전층을 건식식각하는 과정에서 식각된 도전물의 재증착을 이용하여 케소드 측벽에 케소드 팁을 형성한다. 도전물의 재증착에 의해 형성된 케소드 팁의 선단은 선형으로 이루어지기 때문에 점 형상을 갖는 종래의 케소드 팁에 비해 높은 방전효율을 갖는다. 또한, 식각물질과 반응가스에 따라 건식식각 시 재증착이 일어나는 다양한 금속물질을 이용하여 케소드를 형성할 수 있으므로 방전수명이 양호한 금속을 사용하면 특성이 개선된 케소드 팁을 형성할 수 있으며, 저온에서 공정이 진행되므로 유리 기판의 사용도 가능해진다.
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公开(公告)号：KR1020050010661A
公开(公告)日：2005-01-28
申请号：KR1020030050042
申请日：2003-07-22
Applicant: 한국전자통신연구원
IPC: H01L21/22
Abstract: PURPOSE: A lateral diffusion furnace for manufacturing a semiconductor device is provided to load easily a wafer on a boat in a quartz tube by using a tilted opening of the quartz tube and to grow a uniform thin film and minimize the growth of a native oxide layer by preventing an atmospheric gas from permeating into the tube using a tube lid having a gas injection port with a plurality of gas outlet holes. CONSTITUTION: A lateral diffusion furnace includes a reaction chamber(11) with a heating coil(13), a boat(14) for loading wafers(15), a tube and a tube lid. The tube(12) includes a tilted opening(B) for exposing the boat to the outside. The tube lid(20) is used for sealing the tube by covering the opening of the tube. The tube lid includes a gas injection port(17) with a plurality of gas outlet holes(21).
Abstract translation: 目的：提供用于制造半导体器件的横向扩散炉，通过使用石英管的倾斜开口容易地在石英管中的船上加载晶片，并且生长均匀的薄膜并使天然氧化物层的生长最小化 通过使用具有具有多个气体出口孔的气体注入口的管盖来防止大气气体渗透到管中。 构成：横向扩散炉包括具有加热线圈（13）的反应室（11），用于装载晶片（15）的船（14），管和管盖。 管（12）包括用于将船暴露到外部的倾斜开口（B）。 管盖（20）用于通过覆盖管的开口来密封管。 管盖包括具有多个气体出口孔（21）的气体注入口（17）。
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公开(公告)号：KR100418435B1
公开(公告)日：2004-02-14
申请号：KR1020010085165
申请日：2001-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/76
CPC classification number: H01L27/1203 , H01L21/84
Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
Abstract translation: 本发明涉及一种使用SOI结构的衬底制造高压大功率集成电路器件的方法，其中绝缘膜和硅层依次堆叠在硅衬底上。 该方法包括以下步骤：在硅层上顺序形成氧化膜和光致抗蚀剂膜，然后使用沟槽掩模执行光刻工艺以图案化光致抗蚀剂膜; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化物膜，然后去除图案化之后残留的光致抗蚀剂膜; 使用图案化的氧化物膜作为掩模来蚀刻硅层，直到绝缘膜被暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火工艺并且在整个表面上沉积多晶硅以便埋入沟槽; 并依次去除多晶硅和氮化物膜直到硅层暴露以使表面变平，从而形成用于沟槽内器件之间的电隔离的器件隔离膜。 因此，本发明可以有效地减少高压大功率器件与逻辑CMOS器件之间的沟槽的隔离区域，并且可以容易地控制深阱的浓度。
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Patent Agency Ranking
公开(公告)号：KR100403053B1
公开(公告)日：2003-10-23
申请号：KR1020010073392
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/06
Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract translation: 目的：提供一种用于制造双极-CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺制造具有20-30伏和60-90伏的电压容差的BCD器件和不同厚度的栅氧化层 亚微米级的。 构成：在20-30伏特级别的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特的漏极区域下方形成漂移区域，使得阱区域 形成以改善电压容限和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化层变厚，从而提高栅极施加电压以提高驱动能力。 在使用沟槽时，通过隔离设备来减少设备占用面积。 通过使用用于形成双极器件的基极的掩模来形成DMOS器件的漂移区以简化工艺。
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公开(公告)号：KR1020030042654A
公开(公告)日：2003-06-02
申请号：KR1020010073392
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/06
Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract translation: 目的：提供一种用于制造双极CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺来制造电压容差为20-30伏和60-90伏特的不同厚度的栅极氧化物层的BCD器件 的亚微米级。 构成：在20-30伏等级的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特级别的漏极区域形成漂移区域，使得阱区域为 形成以提高耐压性和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化物层变厚，从而增加栅极施加电压以改善驱动能力。 使用沟槽时，通过隔离装置来减少装置占用面积。 形成DMOS器件的漂移区域，以通过使用用于形成双极器件的基极的掩模来简化工艺。
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公开(公告)号：KR1020020090643A
公开(公告)日：2002-12-05
申请号：KR1020010029577
申请日：2001-05-29
Applicant: 한국전자통신연구원
IPC: H01F27/36
Abstract: PURPOSE: A buried inductor for shielding electromagnetic wave and a manufacturing method thereof are provided to improve the performance of an inductor by widely forming a trench on a silicon substrate, depositing a material for shielding the electromagnetic wave on an inner wall of the trench, and burying the inductor. CONSTITUTION: A silicon substrate(21) is provided with a trench. A metal thin film(24) and a magnetic thin films(27,31) are sequentially deposited on a surface of the silicon substrate(21). An inductor coil is formed within the trench. An insulating material(26) is filled in the trench provided with the inductor coil. The inductor coil is comprised of the magnetic thin film(27), a metal layer(30), and the magnetic thin film(31) which are sequentially formed.
Abstract translation: 目的：提供一种用于屏蔽电磁波的埋地电感及其制造方法，以通过在硅衬底上广泛形成沟槽，将用于屏蔽电磁波的材料沉积在沟槽的内壁上，从而提高电感器的性能，以及 埋入电感器。 构成：硅衬底（21）设置有沟槽。 金属薄膜（24）和磁性薄膜（27,31）依次沉积在硅衬底（21）的表面上。 电感线圈形成在沟槽内。 在设置有电感线圈的沟槽中填充绝缘材料（26）。 电感线圈由依次形成的磁性薄膜（27），金属层（30）和磁性薄膜（31）构成。
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公开(公告)号：KR100328126B1
公开(公告)日：2002-08-14
申请号：KR1019980051086
申请日：1998-11-26
Applicant: 한국전자통신연구원
IPC: H01L29/786
Abstract: 액티브 매트릭스 액정 디스플레이( AMLCD : Active Matrix Liquid Crystal Display) 및 EL 디스플레이에서 패널의 픽셀 어레이 스윗치와 주변 구동 집적회로에 이용되는 트렌치 게이트를 구비한 다결정 실리콘 박막 트랜지스터의 제조방법이 개시된다. 본 발명은 실리콘 또는 석영, 유리기판 위에 수평으로 구성되어 있는 게이트 구조를 트렌치 기술을 이용하여 수직으로 게이트를 구성한 트렌치 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터를 제조함으로써, 소자가 차지하는 면적을 줄일 뿐만 아니라 구동 전류의 감소 없이 고 전압에서 동작 할 수 있다
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公开(公告)号：KR1020020054109A
公开(公告)日：2002-07-06
申请号：KR1020000082804
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L27/092
Abstract: PURPOSE: A power device having a trench drain field plate is provided to control extension of space charges at the edge of a gate by including a trench structure in a drift region, and to obtain a breakdown voltage and a low on-resistance by improving reduced surface field(RESURF) effect. CONSTITUTION: A buried layer of the first conductivity type and the epi layer of the second conductivity type are formed on a silicon substrate. A diffusion layer of the first conductivity type as a channel portion is formed on the buried layer. The drift region of the second conductivity type is partially formed on the epi layer. A gate insulation layer is partially formed in the diffusion layer and the drift region. A part of the drift region is formed of a trench structure so that the edge of the gate partially extends in the trench. A drain field plate is formed on an insulation layer having a thickness different from that of the gate insulation layer, connected from the inside of the trench to a drain.
Abstract translation: 目的：提供一种具有沟槽漏极场板的功率器件，以通过在漂移区域中包括沟槽结构来控制栅极边缘处的空间电荷的扩展，并通过改善降低电压来获得击穿电压和低导通电阻 表面场（RESURF）效应。 构成：在硅衬底上形成第一导电类型的掩埋层和第二导电类型的外延层。 作为沟道部分的第一导电类型的扩散层形成在掩埋层上。 第二导电类型的漂移区部分地形成在外延层上。 栅极绝缘层部分地形成在扩散层和漂移区域中。 漂移区的一部分由沟槽结构形成，使得栅极的边缘在沟槽中部分地延伸。 漏极场板形成在绝缘层上，其绝缘层的厚度不同于从沟槽的内部连接到漏极的栅极绝缘层的厚度。
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