公开(公告)号：US20230354503A1

公开(公告)日：2023-11-02

申请号：US18344652

申请日：2023-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/0216 ,  H05K1/024 ,  H01L21/76805 ,  H05K1/0222 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/42 ,  H05K2201/0959 ,  Y10T29/49165 ,  H05K3/4038 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/09645

Abstract: An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

公开(公告)号：US11737205B2

公开(公告)日：2023-08-22

申请号：US17884418

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01L23/552 ,  H05K3/42 ,  H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76805 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0222 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/4038 ,  H05K3/42 ,  H05K2201/0723 ,  H05K2201/0959 ,  H05K2201/09545 ,  H05K2201/09645 ,  Y10T29/49165

Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

公开(公告)号：US20180042123A1

公开(公告)日：2018-02-08

申请号：US15231515

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

公开(公告)号：US09763327B2

公开(公告)日：2017-09-12

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US20170244184A1

公开(公告)日：2017-08-24

申请号：US15422978

申请日：2017-02-02

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H05K1/11 ,  H01R13/405 ,  H01R13/05

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US20170207159A1

公开(公告)日：2017-07-20

申请号：US15477265

申请日：2017-04-03

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/373 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US09686866B2

公开(公告)日：2017-06-20

申请号：US14833129

申请日：2015-08-23

Applicant: Unimicron Technology Corp.

Inventor： Hung-Lin Chang ,  Ta-Han Lin

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/186 ,  H01L23/3121 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2924/15153 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/0333 ,  H05K1/0346 ,  H05K1/111 ,  H05K1/115 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/09081 ,  H05K2201/09545

Abstract: A package structure includes a circuit substrate, at least one electronic component, and a connecting slot. The circuit substrate includes at least one core layer, a build-up structure including at least three patterned circuit layers, at least two dielectric layers and conductive through holes, and circuit pads. The electronic component is embedded in at least one of the dielectric layers and located in a disposition area. The electronic component is electrically connected to one of the patterned circuit layers through a portion of the conductive through holes. The connecting slot has a bottom portion, a plurality of sidewall portions connecting the bottom portion, and a plurality of connecting pads located on the sidewall portions. The circuit substrate is assembled to the bottom portion, and the circuit pads are electrically connected to the connecting pads through a bent area of the core layer that is bent relative to the disposition area.

公开(公告)号：US09668345B2

公开(公告)日：2017-05-30

申请号：US14389387

申请日：2013-03-27

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Hiroyuki Yamaguchi ,  Seiichi Kurihara ,  Hiroshi Sakurai ,  Shunsuke Nukina

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0154 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2201/10287 ,  H05K2203/061 ,  H05K2203/1572

Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.

公开(公告)号：US20160338191A1

公开(公告)日：2016-11-17

申请号：US15096680

申请日：2016-04-12

Applicant: FUJITSU LIMITED

Inventor： Megumi TANAKA ,  Daisuke USUI

IPC: H05K1/02 ,  H05K3/00 ,  H01R12/71 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H01R12/585 ,  H01R12/7082 ,  H01R12/737 ,  H05K1/115 ,  H05K1/142 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2203/0207 ,  H05K2203/1476

Abstract: A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.

Abstract translation: 电路板包括：与第一表面相对的第一表面和第二表面; 在所述第一表面和所述第二表面之间延伸的通孔; 覆盖所述通孔的内壁表面的导体，所述导体的第一端和第二端终止于所述通孔内; 以及连接到所述导体的导线，其中，所述导体与所述导体与所述导体中插入到所述通孔中的连接器针与所述导体的第一端接触的接触部的长度和从所述导体的导线连接部的长度 连接到导体的导线的第二端是0.5mm以下。

公开(公告)号：US09425137B2

公开(公告)日：2016-08-23

申请号：US14552771

申请日：2014-11-25

Applicant: IBIDEN CO., LTD.

Inventor： Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01L23/053 ,  H01L23/12 ,  H05K1/11 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46 ,  H05K1/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/116 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09854 ,  Y10T156/1056

Abstract: A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first, second, third, fourth and fifth insulation layers. The first insulation layer has a first conductor including plating, the second insulation layer has a second conductor including plating, the third insulation layer has a third conductor including conductive paste, the fourth insulation layer has a fourth conductor including plating, the fifth insulation layer has a fifth conductor including plating, and the first conductor, the second conductor, the third conductor, the fourth conductor and the fifth conductor are formed along the same axis and are electrically continuous with each other.

Abstract translation: 布线板包括多个绝缘层，包括以第一，第二，第三，第四和第五绝缘层的顺序层叠的第一，第二，第三，第四和第五绝缘层。 所述第一绝缘层具有包括电镀的第一导体，所述第二绝缘层具有包括电镀的第二导体，所述第三绝缘层具有包括导电糊的第三导体，所述第四绝缘层具有包括电镀的第四导体，所述第五绝缘层具有 包括电镀的第五导体，并且第一导体，第二导​​体，第三导体，第四导体和第五导体沿着相同的轴线形成并且彼此电连接。