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公开(公告)号：KR101829676B1
公开(公告)日：2018-02-20
申请号：KR1020110145765
申请日：2011-12-29
Applicant: 삼성전자주식회사
IPC: H01L21/324
CPC classification number: H01L21/324 , H01L21/67115 , H01L21/67288 , H01L21/681 , H01L22/10 , H01L22/12 , H01L22/20
Abstract: 본발명은웨이퍼열 처리방법을개시한다. 웨이퍼열 처리방법은웨이퍼의결함을검출하는것, 결함이공정챔버내의불균일한온도구배영역들을제외한나머지영역들에위치하도록웨이퍼를정렬하는것, 및공정챔버내에서웨이퍼를급속열처리하는것을포함한다.
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公开(公告)号：KR1020150143187A
公开(公告)日：2015-12-23
申请号：KR1020140072381
申请日：2014-06-13
Applicant: 삼성전자주식회사
Abstract: 본발명의실시예들은전자장치의밀폐진단을위한측정및 분석장치와방법을제공한다. 본발명의일 실시예에따르면, 전자장치의밀폐진단을위한측정장치에있어서, 전자장치의내부기압을측정하는기압센서; 및상기기압센서에서측정된기압정보를무선으로전송하는무선통신부를포함한다.
Abstract translation: 本发明的实施例提供一种用于电子设备的密封诊断的测量和分析装置和方法。 根据本发明的实施例，用于电子设备的密封诊断的测量装置包括：测量电子设备的内部压力的压力传感器; 无线通信单元，其无线地传送从压力传感器测量的压力信息。
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公开(公告)号：KR101414067B1
公开(公告)日：2014-07-02
申请号：KR1020080077531
申请日：2008-08-07
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
Abstract: 반도체 소자의 전극 및 그 형성 방법에서, 반도체 소자의 전극을 형성하기 위하여 기판 상에 불순물이 도핑된 폴리실리콘막을 형성한다. 상기 폴리실리콘막 상에 하드 마스크 패턴을 형성한다. 상기 하드 마스크 패턴을 식각 마스크로 사용하여 상기 폴리실리콘막의 적어도 일부분을 식각함으로써 예비 폴리실리콘 패턴을 형성한다. 상기 예비 폴리실리콘 패턴 표면을 질소와 반응시켜 상기 예비 폴리실리콘 패턴 표면 상에 질화막을 형성한다. 다음에, 상기 하드 마스크 패턴을 식각 마스크로 사용하여 예비 폴리실리콘 패턴을 식각함으로써 폴리실리콘막 패턴을 형성한다. 상기 방법에 의해 전극을 형성하는 경우, 상기 전극에 포함된 폴리실리콘막 패턴의 불순물 확산이 억제된다.
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公开(公告)号：KR1020100033918A
公开(公告)日：2010-03-31
申请号：KR1020090041222
申请日：2009-05-12
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/78696 , H01L21/2255 , H01L29/41725 , H01L29/42312 , H01L29/66348
Abstract: PURPOSE: A recess channel transistor, a method for forming the same, a semiconductor device including the same, and a manufacturing method thereof are provided to reduce a lump failure due to the concentration of an electric field by rounding a recess channel transistor. CONSTITUTION: A recess channel transistor includes a substrate, a gate oxidation layer(158), a gate electrode(162a), a source/drain. The substrate is divided into an active region(150a) and a device isolation region. The active region includes a recess part. The gate oxidation layer is formed on the inner wall of the recess part and the upper side of the substrate. The thickness of the layer in contact with the sidewalls of the recess unit and the active region is 70% thicker than the layer of the layer on the sidewall of the recess unit. The gate electrode is formed on the gate oxidation layer and is positioned inside the recess part. The source/drain is formed under the substrate on both sides of the gate electrode.
Abstract translation: 目的：提供一种凹槽通道晶体管，其形成方法，包括该凹槽通道晶体管的半导体器件及其制造方法，以通过使凹槽沟道晶体管四舍五入来减少由于电场浓度引起的团块故障。 构成：凹槽沟道晶体管包括衬底，栅极氧化层（158），栅电极（162a），源极/漏极。 衬底被分为有源区（150a）和器件隔离区。 有源区域包括凹部。 栅极氧化层形成在凹部的内壁和基板的上侧。 与凹部单元和有源区域的侧壁接触的层的厚度比凹部单元的侧壁上的层的层厚70％。 栅电极形成在栅氧化层上并位于凹部内。 源极/漏极形成在栅极两侧的衬底下方。
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公开(公告)号：KR100785443B1
公开(公告)日：2007-12-13
申请号：KR1020060076025
申请日：2006-08-11
Applicant: 삼성전자주식회사
IPC: H01L21/3065 , H01L21/304
CPC classification number: B08B7/0035 , H01J37/32862
Abstract: An apparatus of cleaning a chamber for fabricating a semiconductor device and a method of cleaning the same are provided to reduce an error rate in a manufacturing process by removing residual by-products in an inside of a chamber. A first plasma supply unit supplies first plasma to an inside of a chamber(102) in order to remove a first product(20) attached on an inner wall of the chamber. A second plasma supply unit supplies second plasma to the inside of the chamber in order to remove a second product(30). An upper electrode(110) and a lower electrode(120) are installed in the inside of the chamber. The first plasma and the second plasma are generated in the inside of the chamber by using the upper electrode and the lower electrode. An analysis unit(150) analyzes components of the first and second plasma. A control unit(160) is connected to the first and second plasma supply units in order to control the first and second plasma supply units according to an analyzed result of the analysis unit.
Abstract translation: 提供一种用于清洁用于制造半导体器件的室的装置及其清洁方法，以通过去除室内的残留副产物来减少制造过程中的错误率。 第一等离子体供应单元将第一等离子体供应到室（102）的内部，以便去除附接在室的内壁上的第一产品（20）。 第二等离子体供应单元将第二等离子体供应到腔室的内部，以便去除第二产品（30）。 上部电极（110）和下部电极（120）安装在腔室的内部。 通过使用上部电极和下部电极，在室内部产生第一等离子体和第二等离子体。 分析单元（150）分析第一和第二等离子体的分量。 控制单元（160）连接到第一和第二等离子体供应单元，以便根据分析单元的分析结果控制第一和第二等离子体供应单元。
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Patent Agency Ranking
公开(公告)号：KR101511933B1
公开(公告)日：2015-04-16
申请号：KR1020080107963
申请日：2008-10-31
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
Abstract: 본 발명의 핀 전계 효과 트랜지스터의 제조 방법은 반도체 기판으로부터 돌출된 핀을 형성하고, 상기 핀의 상부 가장자리를 라운딩시키면서 상기 핀의 상부면과 측면을 덮도록 게이트 절연막을 동시에 형성하되 상기 핀의 상부면 상에 형성되는 상기 게이트 절연막의 두께를 상기 핀의 측면 상에 형성되는 상기 게이트 절연막의 두께보다 두껍게 형성하고, 상기 핀을 가로지르며 상기 게이트 절연막을 덮게 게이트 전극을 형성하는 것을 포함한다.
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公开(公告)号：KR1020130077186A
公开(公告)日：2013-07-09
申请号：KR1020110145765
申请日：2011-12-29
Applicant: 삼성전자주식회사
IPC: H01L21/324
CPC classification number: H01L21/324 , H01L21/67115 , H01L21/67288 , H01L21/681 , H01L22/10 , H01L22/12 , H01L22/20
Abstract: PURPOSE: A wafer heat treating method is provided to prevent a wafer from breaking by performing a rapid heat treatment process after arranging the wafer in order not to position the defect of the wafer at an uneven temperature gradient area in a process chamber. CONSTITUTION: A defect of a wafer is detected. The wafer is arranged in order to position the defect at remaining areas except uneven temperature gradient areas in a process chamber (400). The wafer is rapidly heat-treated in the process chamber. The process chamber has a hexahedron shape of a rectangular cross section. The uneven temperature gradient areas are corner areas of the rectangular cross section.
Abstract translation: 目的：提供晶片热处理方法，以便在布置晶片之后执行快速热处理工艺以防止晶片破裂，以便不将晶片的缺陷定位在处理室中不均匀的温度梯度区域。 构成：检测到晶片缺陷。 布置晶片以将缺陷定位在处理室（400）中除了不均匀的温度梯度区域之外的其余区域。 晶片在处理室中快速热处理。 处理室具有矩形横截面的六面体形状。 不均匀的温度梯度区域是矩形横截面的拐角区域。
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公开(公告)号：KR1020100048690A
公开(公告)日：2010-05-11
申请号：KR1020080107963
申请日：2008-10-31
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7854 , H01L29/66795 , H01L29/42368
Abstract: PURPOSE: A fin field effect transistor and a method for manufacturing the same are provided to prevent the concentration of electric field on the upper edge of a fin by forming a thick gate insulation layer on the upper side of the fin. CONSTITUTION: A fin(3) is protruded from a semiconductor substrate. A gate insulation layer(7) covers the upper side and the lateral side of the fin. A gate electrode(11) covers the gate insulation layer. The upper edge(9) of the fin is a round shape in order to disperse electric field which is applied through the gate electrode. The thickness of the gate insulation layer on the upper side of the fin is thicker than the gate insulation layer on the lateral side of the fin.
Abstract translation: 目的：提供鳍状场效应晶体管及其制造方法，以通过在鳍的上侧形成厚的栅极绝缘层来防止鳍的上边缘上的电场的集中。 构成：翅片（3）从半导体衬底突出。 栅绝缘层（7）覆盖鳍的上侧和外侧。 栅电极（11）覆盖栅极绝缘层。 翅片的上边缘（9）是圆形的，以便分散通过栅电极施加的电场。 翅片上侧的栅极绝缘层的厚度比翅片的侧面上的栅极绝缘层厚。
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公开(公告)号：KR1020100001181A
公开(公告)日：2010-01-06
申请号：KR1020080060998
申请日：2008-06-26
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: H01L21/3185 , H01L21/2236 , H01L21/2652 , H01L21/26546 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/6659
Abstract: PURPOSE: A deposition method for forming a low temperature deposition layer is provided to simplify a process by performing a series processes consecutively through PIIID(Plasma Ion Immersion Implantation and Deposition). CONSTITUTION: In a device, a substrate(100) has a first active region(102) and a second active region(132). A first gate pattern(110) is formed in the first active region. A second gate pattern(140) is formed in the second active region. A first mask film is formed on the substrate in order to expose one of the first and the second active region to the outside. A low doped drain is formed in the first active region adjacent to both side wall of the first gate pattern. A first sacrifice film is formed on the first mask film and the substrate a plasma deposition using PIIID.
Abstract translation: 目的：提供用于形成低温沉积层的沉积方法，以通过PIIID（等离子体离子沉积注入和沉积）连续进行串联处理来简化工艺。 构成：在器件中，衬底（100）具有第一有源区（102）和第二有源区（132）。 在第一有源区中形成第一栅极图案（110）。 在第二有源区中形成第二栅极图案（140）。 在基板上形成第一掩模膜，以将第一和第二有源区域中的一个暴露于外部。 在与第一栅极图案的两个侧壁相邻的第一有源区中形成低掺杂漏极。 在第一掩模膜和基板上使用PIIID形成等离子体沉积的第一牺牲膜。
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公开(公告)号：KR1020080106797A
公开(公告)日：2008-12-09
申请号：KR1020070054666
申请日：2007-06-04
Applicant: 삼성전자주식회사
IPC: H01L21/265
Abstract: A manufacturing method of the semiconductor device is provided to reduce the equivalent thickness of capacitance of the gate insulating layer by maximizing the dosage of the conductive film. A manufacturing method of the semiconductor device comprises the following steps: the step for providing the silicon layer; the step for plasma-doping the silicon layer using the mixed gas of BF3 and B2H6; the step for providing the semiconductor substrate(100) consisting of the single-crystal silicon. The plasma-doping to the silicon layer is to form the reaction layer which is formed by the reaction of the mixed gas consisting of BF3 and B2H6, and the silicon.
Abstract translation: 提供半导体器件的制造方法，以通过使导电膜的用量最大化来减小栅绝缘层的电容的等效厚度。 半导体器件的制造方法包括以下步骤：提供硅层的步骤; 使用BF3和B2H6的混合气体等离子体掺杂硅层的步骤; 提供由单晶硅组成的半导体衬底（100）的步骤。 对硅层的等离子体掺杂是形成通过由BF 3和B 2 H 6组成的混合气体与硅反应而形成的反应层。
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