公开(公告)号：KR100451459B1

公开(公告)日：2004-10-07

申请号：KR1020030008080

申请日：2003-02-10

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  최시영 ,  유종렬 ,  이덕형 ,  정인수

IPC: H01L21/336

CPC classification number: H01L29/78648 ,  H01L21/823437 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/78645

Abstract: A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An insulating coating is formed inside the tunnel. A bottom gate electrode is formed within the insulating coating inside the tunnel. An insulating layer is formed on the substrate and a top gate electrode is formed on the insulating layer opposite the bottom gate electrode.

Abstract translation: 用于场效应晶体管的双栅电极通过在衬底中形成沟槽和从平行于衬底的沟槽的侧壁延伸的隧道来制造。 隧道内形成绝缘涂层。 底部栅电极形成在隧道内的绝缘涂层内。 在衬底上形成绝缘层，并且在与底部栅电极相对的绝缘层上形成顶部栅电极。

公开(公告)号：KR1020030061094A

公开(公告)日：2003-07-18

申请号：KR1020020001463

申请日：2002-01-10

Applicant: 삼성전자주식회사

Inventor： 유종렬 ,  김철성 ,  최시영 ,  박정우 ,  이덕형 ,  이병찬

IPC: H01L29/78

Abstract: PURPOSE: A method for manufacturing a semiconductor device having an elevated junction region is provided to be capable of minimizing the facet phenomenon generated at a region near a gate electrode by using a polysilicon layer. CONSTITUTION: An isolation layer(110) is formed in a semiconductor substrate(100). A gate electrode(140) surrounded with an insulating layer, is formed on the predetermined portion of the semiconductor substrate. A polysilicon layer(150) is formed on the surface of the gate electrode and the isolation layer. An epitaxial growth layer(160) made of a single crystal silicon layer is formed on the exposed portion of the semiconductor substrate by carrying out an epitaxial growth process. Then, the polysilicon layer is removed. After implanting doped dopants into the epitaxial growth layer, the implanted dopants are diffused into the semiconductor substrate.

Abstract translation: 目的：提供一种用于制造具有升高的结区的半导体器件的方法，以能够通过使用多晶硅层来最小化在栅电极附近的区域产生的刻面现象。 构成：在半导体衬底（100）中形成隔离层（110）。 在半导体衬底的预定部分上形成由绝缘层包围的栅电极（140）。 在栅电极和隔离层的表面上形成多晶硅层（150）。 通过进行外延生长工艺，在半导体衬底的暴露部分上形成由单晶硅层制成的外延生长层（160）。 然后，去除多晶硅层。 在将掺杂掺杂剂注入外延生长层之后，注入的掺杂剂扩散到半导体衬底中。

公开(公告)号：KR1020030029211A

公开(公告)日：2003-04-14

申请号：KR1020010061378

申请日：2001-10-05

Applicant: 삼성전자주식회사

Inventor： 허성준 ,  최시영 ,  박정우 ,  윤선필 ,  구자흠 ,  유종렬

IPC: H01L21/28

Abstract: PURPOSE: A contact line in a semiconductor device and a method for forming the same are provided to prevent a leakage current between a contact line and a semiconductor substrate, reducing resistance of the contact line. CONSTITUTION: A gate pattern(130) is formed on the active region of a semiconductor substrate(100). An ion implantation is performed using an ion implantation mask as the gate pattern. An impurity region is formed on the active region. An interlayer dielectric(160) is formed on the entire surface of the resultant structure. A contact hole(170) is formed to expose the active region. An SEG layer is formed on the exposed active region. A silicide layer(190) is formed by a silicidation process. A contact line is formed.

Abstract translation: 目的：提供半导体器件中的接触线及其形成方法，以防止接触线与半导体衬底之间的漏电流，降低接触线的电阻。 构成：在半导体衬底（100）的有源区上形成栅极图案（130）。 使用离子注入掩模作为栅极图案进行离子注入。 在有源区上形成杂质区。 在所得结构的整个表面上形成层间电介质（160）。 形成接触孔（170）以暴露活性区域。 在暴露的有源区上形成SEG层。 通过硅化工艺形成硅化物层（190）。 形成接触线。

公开(公告)号：KR1020030020472A

公开(公告)日：2003-03-10

申请号：KR1020010052396

申请日：2001-08-29

Applicant: 삼성전자주식회사

Inventor： 김철성 ,  최시영 ,  박정우 ,  유종렬 ,  이병찬

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: PURPOSE: A trench isolation type semiconductor device and a method for forming the same are provided to reduce a leakage current by removing defects or dangling bonds of a silicon substrate. CONSTITUTION: A trench etch mask including a pad oxide layer and an etch stop layer is formed on a silicon substrate(10). A trench is formed by etching the substrate(10). A sidewall oxide layer(23) is formed by performing a thermal oxidation process on the substrate(10). A silicon nitride liner(25) is formed by performing a CVD process. A silicon oxide layer is formed on the silicon nitride liner(25). The trench etch mask is exposed by removing the silicon oxide layer formed on the outside of the trench. A trench isolation layer(29) is formed by etching and removing the etch stop layer and the pad oxide layer of the trench etch mask.

Abstract translation: 目的：提供沟槽隔离型半导体器件及其形成方法，以通过去除硅衬底的缺陷或悬挂键来减少漏电流。 构成：在硅衬底（10）上形成包括衬垫氧化物层和蚀刻停止层的沟槽蚀刻掩模。 通过蚀刻衬底（10）形成沟槽。 通过在基板（10）上进行热氧化处理来形成侧壁氧化物层（23）。 通过进行CVD工艺形成氮化硅衬垫（25）。 在氮化硅衬垫（25）上形成氧化硅层。 通过去除形成在沟槽外部的氧化硅层来暴露沟槽蚀刻掩模。 通过蚀刻和去除沟槽蚀刻掩模的蚀刻停止层和焊盘氧化物层来形成沟槽隔离层（29）。

公开(公告)号：KR101628197B1

公开(公告)日：2016-06-09

申请号：KR1020140109653

申请日：2014-08-22

Applicant: 삼성전자주식회사

Inventor： 이현정 ,  구본영 ,  김선정 ,  유종렬 ,  이승훈 ,  탕,포런

IPC: H01L21/8234 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: 반도체소자의제조방법은기판상에채널막을형성하는것, 상기채널막상에희생막을형성하는것, 상기희생막상에하드마스크패턴을형성하는것, 및상기하드마스크패턴을식각마스크로사용하여상기하드마스크패턴에노출된상기희생막및 상기채널막을식각하여, 상기희생막이제거되어상부면이드러난채널부를형성하는것을포함하되, 상기채널막은 SiGe(0≤y

公开(公告)号：KR1020160043206A

公开(公告)日：2016-04-21

申请号：KR1020140136835

申请日：2014-10-10

Applicant: 삼성전자주식회사

Inventor： 유종렬 ,  이현정 ,  김선정 ,  이승훈 ,  최은혜

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/788

CPC classification number: H01L29/1054 ,  H01L21/823412 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/7849 ,  H01L29/785

Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치는제 1 및제 2 영역들의반도체기판상에형성된버퍼층, 상기제 1 영역의상기버퍼층상에형성된제 1 채널층, 상기제 2 영역의상기버퍼층상에형성된제 2 채널층, 및상기제 2 채널층과상기버퍼층사이에배치된스페이서층을포함하되, 상기버퍼층, 상기제 2 채널층, 및상기스페이서층은게르마늄(Ge)을포함하는반도체물질들로형성되며, 상기제 1 채널층과상기제 2 채널층간의게르마늄농도차이는상기버퍼층과상게 2 채널층간의게르마늄농도차이보다크고, 상기스페이서층은게르마늄의농도구배(gradient)를가질수 있다.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括形成在第一和第二区域的半导体衬底上的缓冲层，形成在对应于第一区域的缓冲层上的第一沟道层，形成在对应于第二区域的缓冲层上的第二沟道层，以及 设置在第二沟道层和缓冲层之间的间隔层，其中缓冲层，第二沟道层和间隔层由包含锗（Ge）的半导体材料形成，第一沟道层和第二沟道之间的浓度差 层比缓冲层和第二沟道层之间的层大，并且间隔层可以具有锗的浓度梯度。

公开(公告)号：KR101570044B1

公开(公告)日：2015-11-20

申请号：KR1020090022597

申请日：2009-03-17

Applicant: 삼성전자주식회사

Inventor： 전인상 ,  이시형 ,  유종렬 ,  신유균 ,  최석헌

IPC: H01L21/336 ,  H01L21/8242

CPC classification number: H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

Abstract: 비저항이낮은매립형텅스텐금속게이트제조방법에서, 반도체기판상에게이트형성용리세스를형성하고, 상기게이트형성용리세스에게이트유전막을형성하며, 상기게이트유전막상에배리어금속막을형성하고, 상기배리어금속막상에핵형성용금속층을형성하며, 상기핵형성용금속층을열처리하여저항이낮게상변화를실시하고, 상기상변화된핵형성용금속층을기반으로벌크게이트금속전극을형성한다. 상기핵형성용금속층을열처리하여비저항을낮추고이를기반으로벌크금속게이트전극을형성하면비저항이낮은전기적인특성이우수한반도체장치를만들수 있다.

公开(公告)号：KR1020120003422A

公开(公告)日：2012-01-10

申请号：KR1020110140373

申请日：2011-12-22

Applicant: 삼성전자주식회사

Inventor： 이병학 ,  박희숙 ,  손웅희 ,  유종렬 ,  윤선필 ,  이창원

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/42356 ,  H01L21/76831 ,  H01L29/66712

Abstract: PURPOSE: A buried gate electrode of a transistor and a forming method thereof are provided to prevent an interface oxidation of a silicon pattern by protecting the interface between a silicon pattern and an adhesive layer with a capping layer. CONSTITUTION: An adhesive layer is formed on a silicon layer with a gap area. A tungsten film filling the gap area is formed on the adhesive layer. The upper side of the silicon layer is exposed and a tungsten pattern(62p) filling the gap area and an adhesive pattern(60p) are formed. A capping layer(64) is formed on the front of a substrate(10) with the tungsten pattern and the adhesive pattern. A silicon pattern(58p) is formed by successively patterning the capping layer and the silicon layer.

Abstract translation: 目的：提供晶体管的掩埋栅电极及其形成方法，以通过用覆盖层保护硅图案和粘合剂层之间的界面来防止硅图案的界面氧化。 构成：在具有间隙面积的硅层上形成粘合剂层。 填充间隙区域的钨膜形成在粘合剂层上。 暴露硅层的上侧，形成填充间隙区域的钨图案（62p）和粘合剂图案（60p）。 在具有钨图案和粘合剂图案的衬底（10）的前部形成覆盖层（64）。 通过连续构图封盖层和硅层形成硅图案（58p）。

公开(公告)号：KR1020100096488A

公开(公告)日：2010-09-02

申请号：KR1020090015389

申请日：2009-02-24

Applicant: 삼성전자주식회사

Inventor： 전인상 ,  이시형 ,  유종렬 ,  신유균 ,  최석헌

IPC: H01L21/336 ,  H01L29/78 ,  B82Y40/00

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L21/28202 ,  H01L27/10876 ,  H01L27/11 ,  H01L27/11517 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66348

Abstract: PURPOSE: A semiconductor device which has a recess channel structure is provided to improve the reliability of a semiconductor device by preventing the deterioration of a gate structure due to impurity like fluorine. CONSTITUTION: An active region(102) is restricted to an element isolation region. The active region comprises a trench for forming a recess channel inside. A gate isolation layer(130) is formed on the surface of the trench. A gate electrode layer is formed on the surface of the gate isolation layer and comprises a nano-crystalline structure. A word line(150) is formed on the surface of the gate electrode layer and fills the trench.

Abstract translation: 目的：提供一种具有凹槽结构的半导体器件，以通过防止由于诸如氟的杂质导致的栅极结构的劣化来提高半导体器件的可靠性。 构成：有源区域（102）限于元件隔离区域。 有源区域包括用于在其内形成凹槽通道的沟槽。 栅极隔离层（130）形成在沟槽的表面上。 栅极电极层形成在栅极隔离层的表面上并且包括纳米晶体结构。 在栅电极层的表面上形成字线（150）并填充沟槽。

公开(公告)号：KR1020100001181A

公开(公告)日：2010-01-06

申请号：KR1020080060998

申请日：2008-06-26

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  최시영 ,  박태서 ,  유종렬 ,  강종훈

IPC: H01L21/205

CPC classification number: H01L21/3185 ,  H01L21/2236 ,  H01L21/2652 ,  H01L21/26546 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6659

Abstract: PURPOSE: A deposition method for forming a low temperature deposition layer is provided to simplify a process by performing a series processes consecutively through PIIID(Plasma Ion Immersion Implantation and Deposition). CONSTITUTION: In a device, a substrate(100) has a first active region(102) and a second active region(132). A first gate pattern(110) is formed in the first active region. A second gate pattern(140) is formed in the second active region. A first mask film is formed on the substrate in order to expose one of the first and the second active region to the outside. A low doped drain is formed in the first active region adjacent to both side wall of the first gate pattern. A first sacrifice film is formed on the first mask film and the substrate a plasma deposition using PIIID.

Abstract translation: 目的：提供用于形成低温沉积层的沉积方法，以通过PIIID（等离子体离子沉积注入和沉积）连续进行串联处理来简化工艺。 构成：在器件中，衬底（100）具有第一有源区（102）和第二有源区（132）。 在第一有源区中形成第一栅极图案（110）。 在第二有源区中形成第二栅极图案（140）。 在基板上形成第一掩模膜，以将第一和第二有源区域中的一个暴露于外部。 在与第一栅极图案的两个侧壁相邻的第一有源区中形成低掺杂漏极。 在第一掩模膜和基板上使用PIIID形成等离子体沉积的第一牺牲膜。