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公开(公告)号：KR1020080076420A
公开(公告)日：2008-08-20
申请号：KR1020070016304
申请日：2007-02-16
Applicant: 삼성전자주식회사
CPC classification number: G11C29/48 , G11C29/1201 , G11C2029/2602
Abstract: A semiconductor device having plural memory units and a method of testing the semiconductor device are provided to improve test efficiency of the semiconductor device by reducing required resources in test equipment. A semiconductor device includes plural memory units(101,102,10M) and an input portion(110). Each of the memory units has plural input lines. The input unit provides a corresponding test signal to a corresponding input line of the input lines in the respective memory units, in response to a test enable signal. The input unit includes a buffer unit(112) and a switching unit(114). The buffer units store plural test signals from the test equipment and provide the corresponding test signal to the corresponding input line. The switching unit switches the corresponding test signal to the corresponding input line in response to the test enable signal.
Abstract translation: 提供具有多个存储单元的半导体器件和测试半导体器件的方法，以通过减少测试设备中的所需资源来提高半导体器件的测试效率。 半导体器件包括多个存储器单元（101,102,10M）和输入部分（110）。 每个存储单元具有多个输入线。 响应于测试使能信号，输入单元向相应存储器单元中的输入线的对应输入线提供相应的测试信号。 输入单元包括缓冲单元（112）和切换单元（114）。 缓冲单元存储来自测试设备的多个测试信号，并将相应的测试信号提供给相应的输入线。 开关单元响应于测试使能信号将相应的测试信号切换到相应的输入线。
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公开(公告)号：KR101964085B1
公开(公告)日：2019-07-31
申请号：KR1020110074228
申请日：2011-07-26
Applicant: 삼성전자주식회사
Inventor： 박찬진
IPC: H01L21/8247 , H01L27/115
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公开(公告)号：KR1020130015444A
公开(公告)日：2013-02-14
申请号：KR1020110077439
申请日：2011-08-03
Applicant: 삼성전자주식회사
Inventor： 박찬진
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L21/02071
Abstract: PURPOSE: A nonvolatile memory device and a manufacturing method thereof are provided to easily form a transistor in the device and reliably connect a wire to the transistor. CONSTITUTION: An interlayer dielectric film(112), a first electrode, a second electrode, and a third electrode are formed on a semiconductor substrate(111). The first electrode and the second electrode are extended in a second direction(D2). The first electrode is electrically connected to the second electrode with a bit line(331-333). The first electrode and the second electrode are contacted with a bit line contact(320). The third electrode is extended in a first direction(D1).
Abstract translation: 目的：提供非易失性存储器件及其制造方法，以容易地在器件中形成晶体管并且可靠地将线连接到晶体管。 构成：在半导体衬底（111）上形成层间绝缘膜（112），第一电极，第二电极和第三电极。 第一电极和第二电极沿第二方向（D2）延伸。 第一电极用位线（331-333）与第二电极电连接。 第一电极和第二电极与位线触点（320）接触。 第三电极沿第一方向（D1）延伸。
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公开(公告)号：KR1020130012822A
公开(公告)日：2013-02-05
申请号：KR1020110074228
申请日：2011-07-26
Applicant: 삼성전자주식회사
Inventor： 박찬진
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/101 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L21/76224
Abstract: PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to easily control the property of a channel layer by doping first conductivity type or second conductivity type impurities in the channel layer. CONSTITUTION: An inter-layer insulating layer(112) and a sacrificial layer are successively laminated on a semiconductor substrate(111). A resistance changing layer(141) and a first electrode(147) passing through the inter-layer insulating layer and the sacrificial layer are formed. The upper part of the first electrode is removed to form an upper trench. The upper trench is filled with a channel layer(143). The insulating layer is formed in the channel layer. Second electrodes(211-291,212-292,213-293) are formed on the resistance changing layer.
Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以通过在沟道层中掺杂第一导电类型或第二导电类型的杂质来容易地控制沟道层的性质。 构成：层间绝缘层（112）和牺牲层依次层叠在半导体基板（111）上。 形成穿过层间绝缘层和牺牲层的电阻变化层（141）和第一电极（147）。 去除第一电极的上部以形成上沟槽。 上沟槽填充有沟道层（143）。 绝缘层形成在沟道层中。 第二电极（211-291,212-292,213-293）形成在电阻变化层上。
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公开(公告)号：KR1020120135858A
公开(公告)日：2012-12-17
申请号：KR1020110146159
申请日：2011-12-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L21/76205 , H01L27/0688 , H01L27/11578 , H01L29/7926 , H01L45/04
Abstract: PURPOSE: A nonvolatile memory cell and a non-volatile memory device including the same are provided to improve voltage and current characteristics by including a diffusion barrier film which prevents the diffusion of conducting material. CONSTITUTION: A first inter-layer insulating film(111) and a second inter-layer insulating film(112) are separated each other and are successively laminated. A first electrode(115) passes through the first inter-layer insulating film and the second inter-layer insulating film. A resistance alteration film(116) is formed side by side with the first electrode along the side of the first electrode. A second electrode is formed between the first inter-layer insulating film and the second inter-layer insulating film. A diffusion barrier film prevents the diffusion of conducting material including a conductive film.
Abstract translation: 目的：提供一种非易失性存储单元和包括该非易失性存储单元的非易失性存储器件，以通过包括防止导电材料扩散的扩散阻挡膜来改善电压和电流特性。 构成：第一层间绝缘膜（111）和第二层间绝缘膜（112）彼此分离并依次层叠。 第一电极（115）穿过第一层间绝缘膜和第二层间绝缘膜。 电阻变化膜（116）与第一电极沿着第一电极的侧面并排形成。 在第一层间绝缘膜和第二层间绝缘膜之间形成第二电极。 扩散阻挡膜防止包括导电膜的导电材料的扩散。
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Patent Agency Ranking
公开(公告)号：KR1020120048415A
公开(公告)日：2012-05-15
申请号：KR1020100110033
申请日：2010-11-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926 , H01L27/0207 , H01L27/0688
Abstract: PURPOSE: A 3-dimensional semiconductor device and a manufacturing method thereof are provided to control electrical resistance increase of a current path by directly contacting a semiconductor pattern to entire inner wall of a hole formed on the upper side of a bottom structure. CONSTITUTION: A top structure(20) is arranged on a bottom structure(10). The top structure comprises conductive patterns(230) which are successively laminated. The bottom structure comprises a semiconductor substrate. A semiconductor pattern passes through the top structure and is connected to the bottom structure. A first semiconductor pattern and a second semiconductor pattern form a route(51) which electrically interlinks the top structure and the bottom structure. An insulating spacer is placed between the top structure and the semiconductor pattern.
Abstract translation: 目的：提供三维半导体器件及其制造方法，以通过将半导体图案直接接触形成在底部结构的上侧的孔的整个内壁来控制电流通路的电阻增加。 构成：顶部结构（20）布置在底部结构（10）上。 顶部结构包括依次层压的导电图案（230）。 底部结构包括半导体衬底。 半导体图案通过顶部结构并连接到底部结构。 第一半导体图案和第二半导体图案形成电连接顶部结构和底部结构的路线（51）。 在顶部结构和半导体图案之间放置绝缘间隔物。
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公开(公告)号：KR1020110108219A
公开(公告)日：2011-10-05
申请号：KR1020100064413
申请日：2010-07-05
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11582 , H01L27/1157 , H01L27/0688 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/00 , H01L2924/0002
Abstract: 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 차례로 적층된 도전 패턴들을 포함하면서 기판 상에 배치되는 도전 구조체, 도전 구조체를 관통하여 기판의 상부면에 삽입되는 반도체 패턴, 및 상기 반도체 패턴과 상기 도전 구조체 사이에 개재되는 절연막 구조체를 포함한다. 또한, 반도체 패턴은 절연막 구조체의 아래에서 수평적으로 연장되어 기판의 측벽과 직접 접촉한다.
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公开(公告)号：KR1020100111163A
公开(公告)日：2010-10-14
申请号：KR1020090029588
申请日：2009-04-06
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L21/28282 , H01L27/11568 , H01L27/11578 , H01L29/66833 , H01L29/792 , H01L27/11273
Abstract: PURPOSE: A nonvolatile memory device is provided to minimize the short channel effect of a nonvolatile memory device and to reduce parasitic capacitance and power consumption. CONSTITUTION: A nonvolatile memory device a word line(110) on a substrate(100), an active region(150), and a charge trapping layer. The active region is arranged on the word line and crosses the word line. The charge trapping layer is between the word line and the active region.
Abstract translation: 目的：提供非易失性存储器件以最小化非易失性存储器件的短沟道效应并减少寄生电容和功耗。 构成：非易失性存储器件，衬底（100）上的字线（110），有源区（150）和电荷俘获层。 有源区域布置在字线上并与字线交叉。 电荷捕获层位于字线和有源区之间。
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公开(公告)号：KR1020080051065A
公开(公告)日：2008-06-10
申请号：KR1020070123002
申请日：2007-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2436 , H01L27/2463
Abstract: A flash memory and a driving method thereof are provided to remove interference of adjacent cells by easily depleting a body region of a memory cell formed on a semiconductor pin. A local bit line is connected with a bit line on a semiconductor substrate(110) of first conductive type. A local source line is connected with a common source line crossing the bit line. Plural memory cells are connected parallel with the local source line and the bit line. The local bit line and the local source line are vertically spaced apart from each other in the semiconductor substrate, and include a first doped layer(121) and a second doped layer(122). A first select transistor connects the bit line with the local bit line, and a second select transistor connects the common source line with the local source line. A drain select line(DSL) and a source select line(SSL) are connected to the first select transistor and the second select transistor, respectively. Plural word lines are connected to the memory cells.
Abstract translation: 提供闪速存储器及其驱动方法以通过容易地消耗形成在半导体引脚上的存储单元的体区来消除相邻单元的干扰。 局部位线与第一导电类型的半导体衬底（110）上的位线连接。 本地源极线与穿过位线的公共源极线连接。 多个存储单元与本地源极线和位线并联连接。 局部位线和局部源极线在半导体衬底中彼此垂直间隔开，并且包括第一掺杂层（121）和第二掺杂层（122）。 第一选择晶体管将位线与局部位线连接，第二选择晶体管将公共源极线与本地源极线连接。 漏极选择线（DSL）和源选择线（SSL）分别连接到第一选择晶体管和第二选择晶体管。 多个字线连接到存储单元。
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公开(公告)号：KR102258109B1
公开(公告)日：2021-05-28
申请号：KR1020150080591
申请日：2015-06-08
Applicant: 삼성전자주식회사
Abstract: 반도체소자및 그의형성방법이제공된다. 상기반도체소자는소자분리막상에위치하는게이트어셈블리; 상기게이트어셈블리의측면상에위치하는게이트스페이서; 상기게이트스페이서상에위치하는컨택어셈블리; 상기소자분리막과상기컨택어셈블리사이에위치하는에어갭; 및상기게이트스페이서와상기에어갭 사이에위치하는제 1 스페이서캡핑막을포함한다. 상기제 1 스페이서캡핑막은상기게이트스페이서와식각선택비를갖는다.
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