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公开(公告)号：KR1020150081024A
公开(公告)日：2015-07-13
申请号：KR1020140000572
申请日：2014-01-03
Applicant: 한국전자통신연구원
CPC classification number: H01L33/24 , H01L33/38 , H01L33/64 , H01L2933/0016
Abstract: 본발명은수직형 UV-LED 제조방법을제공한다. 상기방법은기판상에순차적으로적층된버퍼층, n-컨택층및 p-컨택층을포함하는 UV-LED 에피구조를형성하고, 기판으로부터 n-컨택층까지연장한비아홀을형성하고, 비아홀측벽에제공되고상기 n-컨택층에노출되는절연스페이스를형성하고, 그리고비아홀과 n-형컨택층과연결하는금속전극을형성하는공정을수행하는것을포함한다.
Abstract translation: 本发明提供一种制造垂直UV-LED的方法。 该方法包括形成依次层压在基板上的包括缓冲层，n接触层和p接触层的UV-LED外延结构的步骤; 形成从所述基板延伸到所述n接触层的通孔的步骤; 形成设置在所述通孔的侧壁上并暴露于所述n接触层的绝缘空间的步骤; 以及形成将通孔与n接触层连接的金属电极的工序。 因此，该方法能够提高散热性能。
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公开(公告)号：KR101358300B1
公开(公告)日：2014-02-10
申请号：KR1020090125467
申请日：2009-12-16
Applicant: 한국전자통신연구원
IPC: H01L31/0445 , H01L31/0224 , H01L31/0236
CPC classification number: Y02E10/50
Abstract: 본 발명은 CIGS 태양전지 및 그 제조방법이 제공된다. 그의 방법은 다수개의 돌기들이 노출되는 버퍼층을 형성한다. 이후, 버퍼층의 다수개의 돌기를 따라 울퉁불퉁하게 굴곡되는 상부표면을 갖는 윈도우 전극층을 형성한다. 따라서, 윈도우 전극층의 상부표면을 거칠게 가공하기 위한 별도의 가공처리를 요구하지 않기 때문에 생산성을 향상할 수 있다.
버퍼층, 돌기, 난반사, 윈도우(window), 전극-
公开(公告)号：KR1020130085224A
公开(公告)日：2013-07-29
申请号：KR1020120006224
申请日：2012-01-19
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to improve the stability of a T-type gate electrode by providing the high electron mobility transistor including an insulating film having a fine critical dimension. CONSTITUTION: A source electrode (202a) and a drain electrode (202b) are formed on a substrate (201). Insulating layers (203,206,208) including an opening part (209) between the source electrode and drain electrode are formed. The insulating layer comprises silicon nitride film or silicon oxide film. A T-type gate electrode (213) is formed at the upper part of the insulating layer. The body part of the T-type gate electrode is formed at the opening part of the insulating film.
Abstract translation: 目的：提供一种高电子迁移率晶体管及其制造方法，通过提供包括具有细小临界尺寸的绝缘膜的高电子迁移率晶体管来提高T型栅电极的稳定性。 构成：在基板（201）上形成源电极（202a）和漏电极（202b）。 形成包括源电极和漏电极之间的开口部分（209）的绝缘层（203,206,208）。 绝缘层包括氮化硅膜或氧化硅膜。 在绝缘层的上部形成T型栅电极（213）。 T型栅极的主体部分形成在绝缘膜的开口部分。
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公开(公告)号：KR1020130010823A
公开(公告)日：2013-01-29
申请号：KR1020120018591
申请日：2012-02-23
Applicant: 한국전자통신연구원
IPC: H01L29/812 , H01L21/338
Abstract: PURPOSE: A nitride electronic device and a manufacturing method thereof are provided to implement an integrated circuit with various properties on a single substrate by using design technology and unit process with a structure of a different channel layer and a barrier layer. CONSTITUTION: A low temperature buffer layer(102) is formed on a sapphire substrate(101). A first semi-insulating GaN layer(103) is formed on the low temperature buffer layer. A first channel layer(104) for an electron transfer is formed on the first semi-insulating GaN layer. A first barrier layer(105) is formed on the first channel layer. A second semi-insulating GaN layer(107) is formed on the sidewall of the first barrier layer and the first channel layer. A second channel layer(108) and a second barrier layer(109) are formed on the second semi-insulating GaN layer.
Abstract translation: 目的：提供一种氮化物电子器件及其制造方法，通过使用具有不同沟道层和阻挡层的结构的设计技术和单元工艺，在单个衬底上实现具有各种性能的集成电路。 构成：在蓝宝石衬底（101）上形成低温缓冲层（102）。 在低温缓冲层上形成第一半绝缘GaN层（103）。 用于电子转移的第一沟道层（104）形成在第一半绝缘GaN层上。 第一阻挡层（105）形成在第一沟道层上。 在第一阻挡层和第一沟道层的侧壁上形成第二半绝缘GaN层（107）。 在第二半绝缘GaN层上形成第二沟道层（108）和第二势垒层（109）。
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公开(公告)号：KR1020120111525A
公开(公告)日：2012-10-10
申请号：KR1020110030041
申请日：2011-04-01
Applicant: 한국전자통신연구원 , 인하대학교 산학협력단
CPC classification number: H01L33/0075 , H01L33/325
Abstract: PURPOSE: A gallium nitride-based LED and a manufacturing method thereof are provided to improve hole mobility by controlling the doping concentration of an intermediate layer. CONSTITUTION: An n-type nitride semiconductor layer(230) is formed on a substrate. An active layer(240) is formed on the n-type nitride semiconductor layer. A p-type doped intermediate layer(250) is formed on the active layer. A p-type nitride semiconductor layer(260) is formed on the p-type doped intermediate layer. The doping concentration of the p-type doped intermediate layer is lower than the doping concentration of the p-type nitride semiconductor layer. The thickness of the p-type doped intermediate layer is 10 to 100nm.
Abstract translation: 目的：提供一种氮化镓基LED及其制造方法，以通过控制中间层的掺杂浓度来提高空穴迁移率。 构成：在基板上形成n型氮化物半导体层（230）。 在n型氮化物半导体层上形成有源层（240）。 在有源层上形成p型掺杂中间层（250）。 在p型掺杂中间层上形成p型氮化物半导体层（260）。 p型掺杂中间层的掺杂浓度低于p型氮化物半导体层的掺杂浓度。 p型掺杂中间层的厚度为10〜100nm。
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Patent Agency Ranking
公开(公告)号：KR100869962B1
公开(公告)日：2008-11-24
申请号：KR1020060123959
申请日：2006-12-07
Applicant: 한국전자통신연구원
Inventor： 배성범
IPC: H01L33/14
CPC classification number: H01L33/14 , H01L33/20 , H01L33/32 , H01L33/38 , H01L2933/0016
Abstract: 본 발명은 질화물 반도체를 이용한 발광소자의 제조방법에 관한 것으로, 이종 접합 구조를 이용한 n형 및 p형 전류 확산층(current spreading layer)을 형성하는 단계, n형 및 p형 전류 확산층에 건식 식각을 통한 트렌치 형성단계, n형 전류 확산층 내에 형성된 트렌치에 n형 금속 전극을 형성하는 단계, p형 전류 확산층내에 형성된 트렌치에 p형 금속 전극을 형성하는 단계 및 p형 금속 전극층 상에 투명 전극(transparent metal)층을 형성하는 단계를 포함함으로써, 종래의 발광소자 제조방법에 비해 n형 및 p형 전극층에서 전류 확산 특성을 개선하여 발광소자의 동작 특성을 높이기 위한 구조이다.
질화물 반도체, 발광소자, 트렌치, 전류 확산층-
公开(公告)号：KR1020050053992A
公开(公告)日：2005-06-10
申请号：KR1020030087255
申请日：2003-12-03
Applicant: 한국전자통신연구원
Inventor： 배성범
IPC: H01L29/778
Abstract: 게이트 전극의 누설 전류를 방지할 수 있는 이종 접합을 가지는 고전자 이동도 트랜지스터(HEMT)의 제조방법을 개시한다. 개시된 본 발명의 HEMT의 제조방법은 절연 기판상부에 GaN 성분을 포함하는 반절연층을 형성하고, 상기 반절연층 상부에 반도체층을 형성한다음, 상기 반도체층 상부의 소정 부분에 저온 증착 방식에 의해 AlON층을 형성한다. 상기 AlON층 양측의 반도체층 상부에 오믹 콘택층을 형성하고, 상기 AlON층 상부에 쇼트키 콘택층을 형성한다.
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公开(公告)号：KR1020040046479A
公开(公告)日：2004-06-05
申请号：KR1020020074420
申请日：2002-11-27
Applicant: 한국전자통신연구원
IPC: H01L29/772
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of embodying a SAW filter using an Sl(Semi Insulating)-GaN layer of an HEMT(High Electron Mobility Transistor) for integrating the devices on a unit wafer. CONSTITUTION: An HEMT device is manufactured by depositing an SI GaN layer(12) and an AlxGa1-xN layer(13) on a semiconductor substrate(11). The first predetermined region of the AlxGa1-xN layer is etched. An FET(Field Effect Transistor) device is manufactured by forming FET electrodes(14a,14b) on the predetermined region of the AlxGa1-xN layer. The second predetermined region of the AlxGa1-xN layer is etched for exposing the SI GaN layer. Then, a SAW filter is manufactured by forming SAW filter electrodes(15) on the exposed SI-GaN layer.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，其能够使用用于将器件集成在单元晶片上的HEMT（高电子迁移率晶体管）的S1（半绝缘）-GaN层来体现SAW滤波器。 构成：通过在半导体衬底（11）上沉积SI GaN层（12）和Al x Ga 1-x N层（13）来制造HEMT器件。 蚀刻Al x Ga 1-x N层的第一预定区域。 通过在Al x Ga 1-x N层的预定区域上形成FET电极（14a，14b）来制造FET（场效应晶体管）器件。 蚀刻Al x Ga 1-x N层的第二预定区域以暴露SI GaN层。 然后，通过在暴露的SI-GaN层上形成SAW滤波器电极（15）来制造SAW滤波器。
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公开(公告)号：KR100413523B1
公开(公告)日：2004-01-03
申请号：KR1020010079308
申请日：2001-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/778
Abstract: PURPOSE: A method for manufacturing an HEMT(High Electron Mobility Transistor) having the increased electron density of two dimensional electron gas is provided to be capable of improving the high power and frequency characteristics of the transistor without electron scattering by forming a potential well at the bi-junction surface between a GaN layer and an AlxGa1-xN layer at the temperature of 1000°C, or higher. CONSTITUTION: A high resistive GaN layer(62) is formed on a substrate(60). An InN layer(64) is formed on the high resistive GaN layer(62) by In-delta doping using an MOCVD(Metal-Organic Chemical Vapor Deposition) method. At this time, a potential well is formed at the InN layer and an electron density increased two dimensional electron gas layer is capable of being formed at the potential well. An AlxGa1-xN layer(69) is formed on the InN layer(64). Preferably, the substrate is made of one selected from a group consisting of sapphire, SiC, GaN, Si, or GaAs. Preferably, the GaN layer(62) has a thickness of 1-10 μm. Preferably, the GaN, InN, and AlxGa1-xN layer forming processes are carried out at the temperature of 1000°C, or higher.
Abstract translation: 目的：提供一种用于制造具有增加的二维电子气的电子密度的HEMT（高电子迁移率晶体管）的方法，以便能够通过在所述电子阱中形成势阱而改善没有电子散射的晶体管的高功率和频率特性 在1000℃或更高的温度下，在GaN层和Al x Ga 1-x N层之间的双结表面。 构成：在衬底（60）上形成高电阻GaN层（62）。 通过使用MOCVD（金属有机化学气相沉积）方法的In-δ掺杂，在高电阻GaN层（62）上形成InN层（64）。 此时，在InN层上形成势阱，并且势阱中能够形成电子密度增加的二维电子气层。 在InN层（64）上形成Al x Ga 1-x N层（69）。 优选地，衬底由选自蓝宝石，SiC，GaN，Si或GaAs中的一种制成。 优选地，GaN层（62）具有1-10μm的厚度。 优选地，GaN，InN和Al x Ga 1-x N层形成工艺在1000℃或更高的温度下进行。
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公开(公告)号：KR1020030049169A
公开(公告)日：2003-06-25
申请号：KR1020010079308
申请日：2001-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/778
Abstract: PURPOSE: A method for manufacturing an HEMT(High Electron Mobility Transistor) having the increased electron density of two dimensional electron gas is provided to be capable of improving the high power and frequency characteristics of the transistor without electron scattering by forming a potential well at the bi-junction surface between a GaN layer and an AlxGa1-xN layer at the temperature of 1000°C, or higher. CONSTITUTION: A high resistive GaN layer(62) is formed on a substrate(60). An InN layer(64) is formed on the high resistive GaN layer(62) by In-delta doping using an MOCVD(Metal-Organic Chemical Vapor Deposition) method. At this time, a potential well is formed at the InN layer and an electron density increased two dimensional electron gas layer is capable of being formed at the potential well. An AlxGa1-xN layer(69) is formed on the InN layer(64). Preferably, the substrate is made of one selected from a group consisting of sapphire, SiC, GaN, Si, or GaAs. Preferably, the GaN layer(62) has a thickness of 1-10 μm. Preferably, the GaN, InN, and AlxGa1-xN layer forming processes are carried out at the temperature of 1000°C, or higher.
Abstract translation: 目的：提供具有增加的二维电子气体的电子密度的HEMT（高电子迁移率晶体管）的制造方法，以便能够通过在二极管形成电位阱来改善晶体管的高功率和频率特性而不发生电子散射 在1000℃或更高的温度下，GaN层和Al x Ga 1-x N层之间的双结面。 构成：在衬底（60）上形成高电阻GaN层（62）。 通过使用MOCVD（金属有机化学气相沉积）方法的In-δ掺杂，在高电阻GaN层（62）上形成InN层（64）。 此时，在InN层形成势阱，能够在势阱形成电子密度增加的二维电子气层。 在InN层（64）上形成Al x Ga 1-x N层（69）。 优选地，衬底由选自由蓝宝石，SiC，GaN，Si或GaAs组成的组中的一种制成。 优选地，GaN层（62）的厚度为1-10μm。 优选地，GaN，InN和Al x Ga 1-x N层形成工艺在1000℃或更高的温度下进行。
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