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公开(公告)号：KR1020140080575A
公开(公告)日：2014-07-01
申请号：KR1020120144129
申请日：2012-12-12
Applicant: 한국전자통신연구원
CPC classification number: H01L23/66 , H01L23/49844 , H01L2223/6655 , H01L2224/48091 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
Abstract: A package is provided. The package includes a chip plate, a chip mounting plate which is arranged in one side of a ground plate and has an upper surface which is lower than the ground plate, a chip which is mounted on the chip mounting plate, a first input/output terminal which faces the chip mounting plate, is arranged in one side of the ground plate, and is electrically connected to the chip, and a second input/output terminal which faces the ground plate, is arranged in the other side of the chip mounting plate, and is electrically connected to the chip.
Abstract translation: 提供一个包装。 该封装包括芯片板，芯片安装板，其布置在接地板的一侧并具有比接地板低的上表面，安装在芯片安装板上的芯片，第一输入/输出 面向芯片安装板的端子布置在接地板的一侧，并且电连接到芯片，并且面对接地板的第二输入/输出端子布置在芯片安装板的另一侧 并且电连接到芯片。
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公开(公告)号：KR1020140079539A
公开(公告)日：2014-06-27
申请号：KR1020120146836
申请日：2012-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: The present invention relates to a transistor and a method of fabricating the same. A field effect transistor according to one embodiment of the present invention includes a source electrode and a drain electrode which are separated from each other on a substrate; and a + type gate electrode which is arranged on the substrate between the source electrode and the drain electrode. According to one embodiment of the present invention, the + type gate electrode includes a T type gate electrode part; and an additional gate electrode part.
Abstract translation: 晶体管及其制造方法技术领域本发明涉及晶体管及其制造方法。 根据本发明的一个实施例的场效应晶体管包括在基板上彼此分离的源电极和漏电极; 以及配置在源电极和漏电极之间的基板上的+型栅电极。 根据本发明的一个实施例，+型栅电极包括T型栅电极部分; 和附加的栅电极部分。
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公开(公告)号：KR1020140079091A
公开(公告)日：2014-06-26
申请号：KR1020120148675
申请日：2012-12-18
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor is provided. The transistor includes: an active layer and a capping layer which are successively stacked on a substrate; a source ohmic electrode and a drain ohmic electrode which are separated from each other on the capping layer; and a gate electrode which is arranged on the substrate between the source ohmic electrode and the drain ohmic electrode, penetrates the capping layer, and is connected to the active layer. The gate electrode includes a leg part which has a narrow width and is connected to the active layer, and the head part which has a wider width compared to the leg part and is located on the leg part. The leg part of the gate electrode on both end parts of the gate electrode in a direction of extending the gate electrode is narrower than the head part of the gate electrode of the residual part, and is wider than the leg part.
Abstract translation: 提供场效应晶体管。 晶体管包括：有源层和覆盖层，其依次层叠在基板上; 在覆盖层上彼此分离的源欧姆电极和漏极欧姆电极; 并且在源欧姆电极和漏极欧姆电极之间设置在基板上的栅极电极穿过封盖层，并连接到有源层。 栅电极包括具有窄宽度并连接到有源层的脚部，并且头部与腿部相比具有较宽的宽度并且位于腿部上。 栅电极的延伸栅电极方向的两端部的栅极电极的腿部比残留部分的栅电极的头部窄，并且比腿部部分宽。
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公开(公告)号：KR1020130085224A
公开(公告)日：2013-07-29
申请号：KR1020120006224
申请日：2012-01-19
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to improve the stability of a T-type gate electrode by providing the high electron mobility transistor including an insulating film having a fine critical dimension. CONSTITUTION: A source electrode (202a) and a drain electrode (202b) are formed on a substrate (201). Insulating layers (203,206,208) including an opening part (209) between the source electrode and drain electrode are formed. The insulating layer comprises silicon nitride film or silicon oxide film. A T-type gate electrode (213) is formed at the upper part of the insulating layer. The body part of the T-type gate electrode is formed at the opening part of the insulating film.
Abstract translation: 目的：提供一种高电子迁移率晶体管及其制造方法，通过提供包括具有细小临界尺寸的绝缘膜的高电子迁移率晶体管来提高T型栅电极的稳定性。 构成：在基板（201）上形成源电极（202a）和漏电极（202b）。 形成包括源电极和漏电极之间的开口部分（209）的绝缘层（203,206,208）。 绝缘层包括氮化硅膜或氧化硅膜。 在绝缘层的上部形成T型栅电极（213）。 T型栅极的主体部分形成在绝缘膜的开口部分。
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公开(公告)号：KR1020130077432A
公开(公告)日：2013-07-09
申请号：KR1020110146139
申请日：2011-12-29
Applicant: 한국전자통신연구원
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: PURPOSE: An automatic gain control feedback amplifier is provided to freely control a gain even when a difference of an input signal is great. CONSTITUTION: An automatic gain control feedback amplifier (200) includes an amplifier circuit (210), a feedback circuit (220), and a bias circuit (230). The amplifier circuit amplifies a voltage inputted from an input terminal and outputs the voltage to an output terminal. The feedback circuit is connected between the input terminal and the output terminal. The feedback circuit includes a feedback resistor part (221) whose total voltage value is determined by one or more control signals and a feedback transistor connected to the feedback resistor part in parallel. The bias circuit provides a predetermined bias voltage to the feedback transistor.
Abstract translation: 目的：提供一种自动增益控制反馈放大器，即使当输入信号的差异大时也能自由地控制增益。 构成：自动增益控制反馈放大器（200）包括放大器电路（210），反馈电路（220）和偏置电路（230）。 放大器电路放大从输入端子输入的电压，并将该电压输出到输出端子。 反馈电路连接在输入端子和输出端子之间。 反馈电路包括其总电压值由一个或多个控制信号确定的反馈电阻器部分（221）和并联连接到反馈电阻器部分的反馈晶体管。 偏置电路向反馈晶体管提供预定的偏置电压。
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Patent Agency Ranking
公开(公告)号：KR1020130059673A
公开(公告)日：2013-06-07
申请号：KR1020110125763
申请日：2011-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/02 , H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A vertical capacitor and a method for forming the same are provided to be manufactured in a substrate without a separate package. CONSTITUTION: An input electrode(14) and an output electrode(15) are formed in the upper surface(10a) of a substrate(10). A conductive material is formed in a first via hole formed by etching the lower surface(10b) of the substrate. The conductive material is connected to the input electrode and the output electrode. An input via electrode(24) and an output via electrode(25) are formed in the substrate. A dielectric layer(37) is formed between the input via electrode and the via electrode.
Abstract translation: 目的：提供垂直电容器及其形成方法，以便在基板上制造而不需要单独的封装。 构成：在基板（10）的上表面（10a）中形成有输入电极（14）和输出电极（15）。 在通过蚀刻基板的下表面（10b）形成的第一通孔中形成导电材料。 导电材料连接到输入电极和输出电极。 在基板中形成有输入通孔电极（24）和输出通孔电极（25）。 在输入通孔电极和通孔电极之间形成介电层（37）。
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公开(公告)号：KR1020130010823A
公开(公告)日：2013-01-29
申请号：KR1020120018591
申请日：2012-02-23
Applicant: 한국전자통신연구원
IPC: H01L29/812 , H01L21/338
Abstract: PURPOSE: A nitride electronic device and a manufacturing method thereof are provided to implement an integrated circuit with various properties on a single substrate by using design technology and unit process with a structure of a different channel layer and a barrier layer. CONSTITUTION: A low temperature buffer layer(102) is formed on a sapphire substrate(101). A first semi-insulating GaN layer(103) is formed on the low temperature buffer layer. A first channel layer(104) for an electron transfer is formed on the first semi-insulating GaN layer. A first barrier layer(105) is formed on the first channel layer. A second semi-insulating GaN layer(107) is formed on the sidewall of the first barrier layer and the first channel layer. A second channel layer(108) and a second barrier layer(109) are formed on the second semi-insulating GaN layer.
Abstract translation: 目的：提供一种氮化物电子器件及其制造方法，通过使用具有不同沟道层和阻挡层的结构的设计技术和单元工艺，在单个衬底上实现具有各种性能的集成电路。 构成：在蓝宝石衬底（101）上形成低温缓冲层（102）。 在低温缓冲层上形成第一半绝缘GaN层（103）。 用于电子转移的第一沟道层（104）形成在第一半绝缘GaN层上。 第一阻挡层（105）形成在第一沟道层上。 在第一阻挡层和第一沟道层的侧壁上形成第二半绝缘GaN层（107）。 在第二半绝缘GaN层上形成第二沟道层（108）和第二势垒层（109）。
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18.发明授权부정형 고전자이동도 트랜지스터 소자의 제조방법 및 이에 의해 제조된 소자를 갖는 파워 앰프 失效用于制造PSEUDOMORPHIC高电子移动晶体管器件的方法和具有相同产生的PHEM的功率放大器
公开(公告)号：KR101066601B1
公开(公告)日：2011-09-22
申请号：KR1020080118554
申请日：2008-11-27
Applicant: 한국전자통신연구원
IPC: H01L27/04 , H01L29/772
Abstract: 본 발명은 부정형 고전자이동도 트랜지스터의 제조방법 및 이에 의해 제조된 소자를 포함하는 파워 앰프에 관한 것으로, 에피 기판 상에 소오스 및 드레인을 형성하고, 상기 에피 기판을 건식법 및 습식법을 포함하는 게이트 리세스 에칭하여 리세스 영역을 형성하고, 상기 리세스 영역에 게이트를 형성하는 것을 포함하는 방법으로 부정형 고전자이동도 트랜지스터 소자를 제조하는 것을 특징으로 한다.
화합물 반도체 소자, PHEMT, 파워 앰프, 네가티브 피드백 회로-
公开(公告)号：KR1020110024111A
公开(公告)日：2011-03-09
申请号：KR1020090081990
申请日：2009-09-01
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/778 , H01L29/42312 , H01L29/47
Abstract: PURPOSE: A field effect transistor and a manufacturing method thereof are provided to form the field effect transistor of a depletion mode and the field effect transistor of an increase mode on the same substrate by controlling a diffusion depth of the lowermost metal layers. CONSTITUTION: A first gate electrode and a second gate electrode are formed on a Schottky barrier(106). The first gate electrode includes a first lowermost metal layer(120a). The second gate electrode is separated from the first gate electrode and includes a second lowermost metal layer(120b). A first diffusion layer and a second diffusion layer are formed on the first and second lowermost metal layers by thermally processing the substrate.
Abstract translation: 目的：提供一种场效应晶体管及其制造方法，通过控制最下层金属层的扩散深度，在同一基板上形成耗尽型场效应晶体管和增加型场效应晶体管。 构成：在肖特基势垒（106）上形成第一栅电极和第二栅电极。 第一栅电极包括第一最下金属层（120a）。 第二栅电极与第一栅电极分离，并包括第二最下金属层（120b）。 通过热处理基板，在第一和第二最下层金属层上形成第一扩散层和第二扩散层。
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公开(公告)号：KR100942698B1
公开(公告)日：2010-02-16
申请号：KR1020070126841
申请日：2007-12-07
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
Abstract: 본 발명은 다층의 금속 배선 제조 방법에 관한 것으로서, 다층의 감광막을 이용한 리소그라피 공정과, 감광막과 절연막의 식각선택비를 이용하여 절연막 위에 다층의 금속 배선을 형성함으로써, 비아 홀(Via-Hole)과 배선 금속 증착을 위한 리소그라피 공정을 별도로 진행하지 않고, 한 번의 리소그라피 공정으로 진행할 수 있으며, 한 번의 노광을 통해 패턴이 형성됨으로써 오 정렬의 가능성을 줄일 수 있으며, 보다 간단하고, 안정적으로 다층의 금속 배선을 제작할 수 있다.
반도체 기판, 다층의 금속 배선, 다층의 감광막, 오믹금속층, 절연막, 감광막 패턴, 식각 공정, 리프트 오프 공정, 식각마스크.
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