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    Si/SiGe HETEROSTRUCTURE FOR HIGH-SPEED COMPOSITE P-CHANNEL FIELD EFFECT DEVICE
    11.
    发明专利
    Si/SiGe HETEROSTRUCTURE FOR HIGH-SPEED COMPOSITE P-CHANNEL FIELD EFFECT DEVICE 失效

    公开(公告)号：JP2000286413A

    公开(公告)日：2000-10-13

    申请号：JP2000065262

    申请日：2000-03-09

    Applicant: IBM

    Inventor： CHU JACK OON ,  HAMMOND RICHARD ,  ISMAIL KHALID EZZELDIN ,  KOESTER STEVEN JOHN ,  MOONEY PATRICIA MAY ,  OTT JOHN A

    IPC: H01L29/161 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812

    Abstract: PROBLEM TO BE SOLVED: To make applicable the structure of an epitaxial field effect transistor to the intended uses of high-speed low-noise microwave and quasi-millimetric- wave devices, etc., by integrating into the epitaxial field effect transistor a silicon layer, a germanium layer, and silicon-germanium layers which form jointly a modulatorily doped heterostructure. SOLUTION: After forming on a single-crystal semiconductor substrate 11 a buffer layer 12 including a layer 12A, a layer 12B, and a layer 12C, a p-type doped relaxation silicon-germanium layer 13 is formed on the layer 12C of the buffer layer 12. Then, thereon, as a spacer, a non-doped strained silicon layer 14 is grown epitaxially to grow further on the layer 14 epitaxially a non-doped thin relaxation silicon-germanium layer 15. Subsequently, on the layer 15, there are grown epitaxially in succession a germanium layer 16, a silicon-germanium layer 17, and a silicon-germanium cap layer 18 to form the laminated layer of them.

    METHOD FOR FORMING STRAIN LAYER ON INSULATOR
    12.
    发明专利
    METHOD FOR FORMING STRAIN LAYER ON INSULATOR 失效

    公开(公告)号：JPH10308503A

    公开(公告)日：1998-11-17

    申请号：JP11647398

    申请日：1998-04-27

    Applicant: IBM

    Inventor： CHU JACK OON ,  KUHARID ESELDIN ISMAIL

    IPC: H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/12

    Abstract: PROBLEM TO BE SOLVED: To form Si and SiGe layers on an insulation board. SOLUTION: As for an SOI board and a method for forming an SOI board, at first, Si and/or SiGe strain layers 16, 17 are formed on a first board 12. Then, Si and/or SiO2 layers 18 are formed on the strain layers 16, 17 and a second board 19 with an insulator layer in an upper surface is joined to an upper surface of the strain layer 17. Thereafter, the first board 12 is removed. As a result, a problem for forming a strain Si layer and an SiGe layer on an insulation board is solved.

    13.
    发明专利
    未知

    公开(公告)号：DE69733389T2

    公开(公告)日：2006-04-27

    申请号：DE69733389

    申请日：1997-08-06

    Applicant: IBM

    Inventor： CHU JACK OON ,  ISMAIL KHALID EZZELDIN ,  LEE KIM YANG

    IPC: H01L29/165 ,  H01L39/22 ,  H01L29/161 ,  H01L29/80 ,  H01L39/00 ,  H01L39/02 ,  H01L39/12 ,  H01L39/24

    Abstract: A structure based on strained Si/SiGe that has high temperature superconductivity is disclosed. The structure for carrying superconducting current includes a substrate (12); a first epitaxial P type semiconductor layer (14), which is under compressive strain, for transporting holes; a second epitaxial barrier layer (20) positioned on the first layer (14); and a third epitaxial N type semiconductor layer (24), which is under tensile strain, for transporting electrons. The barrier layer (30) is thick enough to restrict recombination of electrons and holes, yet the barrier layer (30) is thin enough to permit coulomb force attraction between the electrons and holes to form electron-hole pairs. The first and second layers (14,20) include SiGe, such as Si1.xGex, where x is 0.6-0.8 for the first layer (14), and 0.3-0.4 for the second layer (20). The third layer (24) includes Si.

    15.
    发明专利
    未知

    公开(公告)号：DE19515346C2

    公开(公告)日：1997-04-17

    申请号：DE19515346

    申请日：1995-04-26

    Applicant: IBM

    Inventor： CABRAL JUN CYRIL ,  CHAN KEVIN KOK ,  CHU JACK OON ,  HARPER JAMEX MCKELL EDWIN

    IPC: C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  C30B25/04 ,  C30B23/04 ,  C30B29/08 ,  C30B29/36

    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium and then growing the epitaxial layer over the wafer at temperatures below 650 DEG C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650 DEG C. by providing a lower temperature process.

    16.
    发明专利
    未知

    公开(公告)号：DE69941588D1

    公开(公告)日：2009-12-10

    申请号：DE69941588

    申请日：1999-02-18

    Applicant: IBM

    Inventor： CHU JACK OON ,  ISMAIL KHALID EZZELDIN ,  KOESTER STEVEN JOHN ,  KLEPSER BERND-ULRICH H

    IPC: H01L27/144 ,  H01L31/10 ,  H01L31/0312 ,  H01L31/0352

    Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

    17.
    发明专利
    未知

    公开(公告)号：DE69836654D1

    公开(公告)日：2007-02-01

    申请号：DE69836654

    申请日：1998-06-26

    Applicant: IBM

    Inventor： CARDONE FRANK ,  CHU JACK OON ,  ISMAIL KHALID EZZELDIN

    IPC: H01L21/205 ,  H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/10 ,  H01L29/36 ,  H01L29/772 ,  H01L29/778 ,  H01L29/812

    Abstract: A structure and method of forming an abrupt doping profile are described. A perferred embodiment incorporates a substrate 32, a first epitaxial layer 36 of Ge less than the critical thickness and having a P or As concentration greater than 5x10 atoms/cc, and a second epitaxial layer 40 having a change in concentration in its first 40 ANGSTROM from the first layer of greater than 1x10 P atoms/cc. In another preferred embodiment, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention addresses the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.

    18.
    发明专利
    未知

    公开(公告)号：DE69733389D1

    公开(公告)日：2005-07-07

    申请号：DE69733389

    申请日：1997-08-06

    Applicant: IBM

    Inventor： CHU JACK OON ,  ISMAIL KHALID EZZELDIN ,  LEE KIM YANG

    IPC: H01L39/22 ,  H01L29/161 ,  H01L29/165 ,  H01L29/80 ,  H01L39/02 ,  H01L39/12 ,  H01L39/24 ,  H01L39/00

    Abstract: A structure based on strained Si/SiGe that has high temperature superconductivity is disclosed. The structure for carrying superconducting current includes a substrate (12); a first epitaxial P type semiconductor layer (14), which is under compressive strain, for transporting holes; a second epitaxial barrier layer (20) positioned on the first layer (14); and a third epitaxial N type semiconductor layer (24), which is under tensile strain, for transporting electrons. The barrier layer (30) is thick enough to restrict recombination of electrons and holes, yet the barrier layer (30) is thin enough to permit coulomb force attraction between the electrons and holes to form electron-hole pairs. The first and second layers (14,20) include SiGe, such as Si1.xGex, where x is 0.6-0.8 for the first layer (14), and 0.3-0.4 for the second layer (20). The third layer (24) includes Si.

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