公开(公告)号：CA2719727A1

公开(公告)日：2009-12-17

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J17/00 ,  H02J7/00 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

公开(公告)号：CZ20011964A3

公开(公告)日：2001-11-14

申请号：CZ20011964

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

公开(公告)号：AT503252T

公开(公告)日：2011-04-15

申请号：AT07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

公开(公告)号：PL348501A1

公开(公告)日：2002-05-20

申请号：PL34850199

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

公开(公告)号：BR9304315A

公开(公告)日：1994-05-31

申请号：BR9304315

申请日：1993-10-21

Applicant: IBM

Inventor： BUTI TAQI N ,  HSU LOUIS ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/90 ,  H01L21/283

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：CA2719727C

公开(公告)日：2017-01-03

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J50/20 ,  H02J7/00 ,  H02J50/80 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

公开(公告)号：DE60030467T2

公开(公告)日：2007-05-03

申请号：DE60030467

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

公开(公告)号：CZ295847B6

公开(公告)日：2005-11-16

申请号：CZ20011964

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: In the present invention, there is disclosed a memory device (200) in a substrate having a trench with side walls in the substrate, said memory device (200) including bit line conductors (246) and word line conductors (230). Signal storage node has a first electrode (202), a second electrode (204) formed within the trench (252; DT), and a node dielectric (206) formed between the electrodes (202, 204). The signal transfer device has: an annular signal transfer region (222) with outer surface adjacent side walls (212) of the trench (252; DT), an inner surface, a first and a second end; a first diffusion region (218) coupling the first end of the signal transfer region (222) to the second electrode (204) of the signal storage node; a second diffusion region (220) coupling the second end of signal transfer region (222) to the bit line conductor (246); a gate insulator (224) coating the inner surface of signal transfer region (222); and a gate conductor (226) coating the gate insulator (224) and coupled to the word line conductor (230). A conductive connecting member (236) couples the signal transfer region (222) to a reference voltage.

公开(公告)号：AT490555T

公开(公告)日：2010-12-15

申请号：AT06819175

申请日：2006-10-27

Applicant: IBM

Inventor： HSU LOUIS ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.

公开(公告)号：AT477588T

公开(公告)日：2010-08-15

申请号：AT05808156

申请日：2005-11-16

Applicant: IBM

Inventor： BURRELL LLOYD ,  CHEN HOWARD ,  HSU LOUIS ,  SAUTER WOLFGANG

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/538

Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.