-
公开(公告)号：CA3127849A1
公开(公告)日：2020-08-06
申请号：CA3127849
申请日：2020-01-23
Applicant: IBM
Inventor： GIAMEI BRUCE CONRAD , KLEIN MATTHIAS , SLEGEL TIMOTHY , FARRELL MARK , SOFIA ANTHONY THOMAS , WEISHAUPT SIMON , MISHRA ASHUTOSH
IPC: G06F9/30
Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general- purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performedby the instruction being a compression functionor a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.
-
公开(公告)号：GB2529425A
公开(公告)日：2016-02-24
申请号：GB201414711
申请日：2014-08-19
Applicant: IBM
Inventor： HAGSPIEL NORBERT , KLEIN MATTHIAS , JUNGHANS SASCHA , WALTER JOERG , AMBROLADZE ELATEROMA M
IPC: G06F13/28
Abstract: A data processing apparatus 1 comprises: a number of processor cores 2a, 2b; a shared processor cache 3 connected to each of the processor cores and to a main memory 6; a bus controller 4 connected to the shared processor cache and configured, in response to receiving a descriptor sent S100, S105, S140 by one of the processor cores, to perform a transfer S155 of requested data indicated by the descriptor from the shared processor cache to an I/O device 7; a bus unit 5 connected to the bus controller and configured for transferring data to/from the I/O device; where the shared processor cache comprises means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access S125 in response to receiving a descriptor from one of the processor cores. The descriptor may comprise address and length information. Efficient data transfer with reduced latency is facilitated.
-
公开(公告)号：GB2456618A
公开(公告)日：2009-07-22
申请号：GB0822285
申请日：2008-12-08
Applicant: IBM
Inventor： KOENIG ANDREAS , KLEIN MATTHIAS , WALZ MANFRED , BUECHNER THOMAS
IPC: G06F11/07
Abstract: Disclosed is a method and circuit for operating self-checking logic 16, 18, 28 in a computer processing chip 10. The chip has functional units for detecting errors 28, for tracing the errors 18, and for controlling the processor clock 16, such that a clock-stop signal is generated by the self-checking logic which is used for error management and recovery. When a stop-clock signal is generated the signal is intercepted 440, a delay 445 is defined during which error-related, chip internal error handling and/ or recovery preparation actions are processed 470. At the end of the predetermined delay 460 the clock-stop action is performed 490, 495. A warning message to firmware may be sent to help in error and recovery management. The delay may be configured according to the location of the failure, the time needed to communicate with the stop-clock signal to the clock mechanism on the chip and/or the time needed to collect and store debug data.
-
公开(公告)号：MX393188B
公开(公告)日：2025-03-24
申请号：MX2021010029
申请日：2021-08-19
Applicant: IBM
Inventor： SOFIA ANTHONY THOMAS , MISHRA ASHUTOSH , JACOBI CHRISTIAN , BHATTACHARJEE DEEPANKAR , KURUP GIRISH GOPALA , BRADBURY JONATHAN , KLEIN MATTHIAS
Abstract: Un aspecto incluye una arquitectura de sistema que incluye una unidad de procesamiento, un acelerador, una memoria intermedia de fuente principal, una memoria intermedia diana principal, y un bloque de memoria. La memoria intermedia de fuente principal almacena una primera parte de un símbolo de fuente recibido de una fuente externa. La memoria intermedia diana principal almacena un símbolo de salida recibido del acelerador. El bloque de memoria incluye una memoria intermedia de fuente de sobreflujo que almacena la primera parte del símbolo de fuente recibido de la memoria intermedia de fuente principal. El acelerador recupera la primera parte del símbolo de fuente almacenado en la memoria intermedia de fuente de sobreflujo y una segunda parte del símbolo de fuente almacenado en la memoria intermedia de fuente principal, y convierte la primera y segunda parte del símbolo de fuente conjuntamente en el símbolo de salida. La segunda parte del símbolo de fuente incluye una parte del símbolo de fuente no incluida en la primera parte del símbolo de fuente.
-
公开(公告)号：AU2020213829B2
公开(公告)日：2022-09-15
申请号：AU2020213829
申请日：2020-01-14
Applicant: IBM
Inventor： RAISCH CHRISTOPH , KRAEMER MARCO , LEHNERT FRANK , KLEIN MATTHIAS , BRADBURY JONATHAN , JACOBI CHRISTIAN , BELMAR BRENTON , DRIEVER PETER
Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).
-
Patent Agency Ranking
公开(公告)号：CA3131257A1
公开(公告)日：2020-09-03
申请号：CA3131257
申请日：2020-02-27
Applicant: IBM
Inventor： KURUP GIRISH GOPALA , KLEIN MATTHIAS , SOFIA ANTHONY THOMAS , BRADBURY JONATHAN , MISHRA ASHUTOSH , JACOBI CHRISTIAN , BHATTACHARJEE DEEPANKAR
IPC: H03M7/40
Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.
-
公开(公告)号：CA3127852A1
公开(公告)日：2020-08-06
申请号：CA3127852
申请日：2020-01-14
Applicant: IBM
Inventor： RAISCH CHRISTOPH , KRAEMER MARCO , LEHNERT FRANK , KLEIN MATTHIAS , BRADBURY JONATHAN , JACOBI CHRISTIAN , BELMAR BRENTON , DRIEVER PETER
Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.
-
公开(公告)号：GB2466222B
公开(公告)日：2013-11-13
申请号：GB0822763
申请日：2008-12-15
Applicant: IBM
Inventor： KLEIN MATTHIAS , ZILLES GERHARD , WALZ MANFRED , GENTNER THOMAS , WAGNER ANDREAS , KOENIG ANDREAS
IPC: G06F9/50 , G06F11/07 , G06F13/20 , H04L12/841
-
公开(公告)号：GB2466222A
公开(公告)日：2010-06-16
申请号：GB0822763
申请日：2008-12-15
Applicant: IBM
Inventor： KLEIN MATTHIAS , ZILLES GERHARD , WALZ MANFRED , GENTNER THOMAS , WAGNER ANDREAS , KOENIG ANDREAS
Abstract: Disclosed is a system for managing the resources processing data transfers in a transaction based input/output chip of a computer system. A transaction is associated with a resource, 18 the transaction being a request packet and a corresponding response packet. The system has a transaction table 10 for holding one resource for each request until the resource has been processed and a resource management 12 for storing information about the availability of these resources, which has become available before a predetermined timeout period T has been exceeded. The system has a FIFO (first-in first-out) memory 14 for buffering those resources, which have been made available after the first timeout period and a second timeout period Q have been exceeded. An arbiter circuit 16 for chooses the resources from the resource management, if any are available, if not the timed-out resources from the FIFO memory are used.
-
20.发明专利
公开(公告)号：GB2456403A
公开(公告)日：2009-07-22
申请号：GB0822313
申请日：2008-12-08
Applicant: IBM
Inventor： KOENIG ANDREAS , SCHLIPF THOMAS , KLEIN MATTHIAS , WALZ MANFRED , FRITZ ROLF
IPC: G06F11/07
Abstract: A method of operating self-testing logic in a tree-like multi-chip processor cluster which generates an infrastructure signal 430, such as a clockstop or tracestop signal, used for error management and recovery. The operation intercepts 440 the infrastructure signal of a processor of the cluster then extracts error information from the infrastructure signal. Using the error information a pre-defined inter-chip error synchronisation scheme is selected 450 including clock-stop and/or trace-stop information for a respective one of the processors of the cluster. Notification signals are distributed 490 to chips of the cluster using dedicated wires or a low-level standard interface for chip-to-chip communication to prepare and execute error related internal operations for chips. On receipt of one of the notification signals a chip performs at least one of (i) performing a trace-stop command or (ii) performing a clock-stop command 495 on a respective one of the chips as derived from the synchronisation scheme. The synchronisation scheme may comprise a configurable delay adjustable according to the location of the failure within the chip.
-
-
-
-
-
-
-
-
-
Search Results
37
records
(took 0.026 seconds)
