公开(公告)号：CA1079683A

公开(公告)日：1980-06-17

申请号：CA275384

申请日：1977-03-30

Applicant: IBM

Inventor： FENG BAI-CWO ,  LECHATON JOHN S

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  C23C15/00

Abstract: FORMING FEEDTHROUGH CONNECTIONS FOR MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEMS A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.

公开(公告)号：FR2349956A1

公开(公告)日：1977-11-25

申请号：FR7705185

申请日：1977-02-18

Applicant: IBM

Inventor： HAVAS JANOS ,  LECHATON JOHN S ,  LOGAN JOSEPH S

IPC: H05K3/46 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H05K3/14 ,  H01L21/441 ,  H01L23/54

Abstract: A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.

公开(公告)号：DE2709986A1

公开(公告)日：1977-11-17

申请号：DE2709986

申请日：1977-03-08

Applicant: IBM

Inventor： HAVAS JANOS ,  LECHATON JOHN S ,  LOGAN JOSEPH SKINNER

IPC: H05K3/46 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H05K3/14 ,  H01L49/02 ,  H01L21/314

Abstract: A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.

公开(公告)号：DE69026460T2

公开(公告)日：1996-10-10

申请号：DE69026460

申请日：1990-08-29

Applicant: IBM

Inventor： LECHATON JOHN S ,  SCHEPIS DOMINIC J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82

Abstract: In a method for manufacturing a BiCMOS device the steps of : providing a semiconductor substrate (22) including first and second electrically isolated device regions (42, 40), forming a layer (50) of insulating material over the first device region and a layer (58), of conductive material conformally over the device. Portions of the conductive layer are removed to leave a base contact (58B) on the surface of the second device region and an insulated gate contact (58A) over the surface of the first device region. A FET is formed in the first device region (42), having a channel under the insulated gate (58A). A vertical bipolar transistor is formed in the second device region (40) having a base region (69, 80) contacting the base contact (58B).

公开(公告)号：DE69026460D1

公开(公告)日：1996-05-15

申请号：DE69026460

申请日：1990-08-29

Applicant: IBM

Inventor： LECHATON JOHN S ,  SCHEPIS DOMINIC J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82

Abstract: In a method for manufacturing a BiCMOS device the steps of : providing a semiconductor substrate (22) including first and second electrically isolated device regions (42, 40), forming a layer (50) of insulating material over the first device region and a layer (58), of conductive material conformally over the device. Portions of the conductive layer are removed to leave a base contact (58B) on the surface of the second device region and an insulated gate contact (58A) over the surface of the first device region. A FET is formed in the first device region (42), having a channel under the insulated gate (58A). A vertical bipolar transistor is formed in the second device region (40) having a base region (69, 80) contacting the base contact (58B).

公开(公告)号：DE3784117D1

公开(公告)日：1993-03-25

申请号：DE3784117

申请日：1987-07-14

Applicant: IBM

Inventor： BONDUR JAMES ALLAN ,  GIAMMARCO NICHOLAS JAMES ,  HANSEN THOMAS ADRIAN ,  KAPLITA GEORGE ANTHONY ,  LECHATON JOHN S

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/263

Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a fluorochlorohydrocarbon (e.g., CCl2F2, CHCl2F2, CCl4 or CCl3F), SF6, O2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the fluorochlorocarbon to SF6 and the following composition: 1-4 % of SF6, 3-10 % of O2, 74-93 % of He and 3-10 % of fluorochlorohydrocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

公开(公告)号：DE3380837D1

公开(公告)日：1989-12-14

申请号：DE3380837

申请日：1983-05-19

Applicant: IBM

Inventor： LECHATON JOHN S ,  MALAVIYA SASHI DHAR ,  SCHEPIS DOMINIC JOSEPH ,  SRINIVASAN GURUMAKONDA RAMASAM

IPC: H01L27/00 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/306

Abstract: @ A fully isolated dielectric structure for isolating regions (14) of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation (18) with pairs of parallel, anisotropic etched trenches (20) which are subsequently oxidized and filled to give complete dielectric isolation for regions (14) of monocrystalline silicon. The anisotropic etching preferably etches a buried N + sublayer (12) under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches (20).

公开(公告)号：DE2860318D1

公开(公告)日：1981-02-19

申请号：DE2860318

申请日：1978-11-30

Applicant: IBM

Inventor： BIALKO JOSEPH ALFON ,  LECHATON JOHN S

IPC: C23C14/04 ,  C23C14/34 ,  C23C14/40 ,  C23C14/44 ,  C23C14/50 ,  H01J37/34

Abstract: Isolating the anode shield of RF sputtering apparatus from the ground potential reduces the grounded surfaces to which the plasma is exposed and thereby increases the impedance between the plasma and the grounded surfaces. This improvement increases the resputtering rate significantly before the operating point of instability in the system is reached.

公开(公告)号：DE3380431D1

公开(公告)日：1989-09-21

申请号：DE3380431

申请日：1983-02-23

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  DORLER JACK ARTHUR ,  GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  MOSLEY JOSEPH MICHAEL ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82 ,  H01L27/06

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.

公开(公告)号：CA1062658A

公开(公告)日：1979-09-18

申请号：CA275385

申请日：1977-03-30

Applicant: IBM

Inventor： HAVAS JANOS ,  LECHATON JOHN S ,  LOGAN JOSEPH S

IPC: H05K3/46 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H05K3/14 ,  C23C15/00

Abstract: MAKING COPLANAR LAYERS OF THIN FILMS A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.