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    Handling an input/output store instruction
    11.
    发明专利
    Handling an input/output store instruction 未知

    公开(公告)号：AU2020214661B2

    公开(公告)日：2022-09-22

    申请号：AU2020214661

    申请日：2020-01-14

    Applicant: IBM

    Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

    IPC: G06F9/30 ,  G06F13/00 ,  G06F13/20

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.

    High availability, high precision system clock register arrangement
    13.
    发明专利
    High availability, high precision system clock register arrangement 未知

    公开(公告)号：GB2489307A

    公开(公告)日：2012-09-26

    申请号：GB201204158

    申请日：2012-03-09

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  ENGLER EBERHARD ,  BUTTLAR JOACHIM VON ,  MEISSNER KLAUS ,  LEHNERT FRANK

    IPC: G06F1/14 ,  G06F11/16

    Abstract: A time of day (TOD) system clock associated with a processing core (2) comprises a host clock register (5) incremented by means of a high precision oscillator (3) and a firmware clock register (6), incremented every time the host clock register (5) is incremented. The system monitors for failures of the host clock register (5), and during a failure of the host clock register (5) increments the firmware clock register (6) by means of timing signals of the processing core (2). Upon receiving a clock value read request providing the content of the host clock register (5) if no failure is detected and updating the firmware clock register (6) with the value of the host clock register (5).

    Controlling timeouts of an error recovery procedure in a digital circuit
    17.
    发明专利
    Controlling timeouts of an error recovery procedure in a digital circuit 未知

    公开(公告)号：GB2456656A

    公开(公告)日：2009-07-29

    申请号：GB0822778

    申请日：2008-12-15

    Applicant: IBM

    Inventor： MAYER ULRICH ,  LEHNERT FRANK ,  GERWIG GUENTER ,  SWANEY SCOTT BARNETT

    IPC: G06F11/07 ,  G06F9/38

    Abstract: The invention relates to apparatus for controlling timeouts and delays of an error recovery procedure in a digital circuit, e.g. a microprocessor. The apparatus comprises a finite state machine (FSM) 10, having a plurality of states 12 and a plurality of transitions 14. Transitions 14 are arranged between two states 12 respectively. States 12 correspond with operation steps (40, 44, 52, 56, 58, 64) of the error recovery procedure, including error classification, a drain operation, a fence operation in which a microprocessor core does not communicate with memory, a reset or refresh operation, and automatic built-in self test (ABIST). Transitions 14 of the FSM 10 depend on conditions (46, 50, 53, 57, 59, 62) for the error recovery procedure. The FSM 10 is coupled with a timeout logic circuit 20 which controls a timer to obtain the timeouts (46, 53, 57, 59) of the error recovery procedure. The FSM is configurable by a data vector which describes states 12 of the FSM for which the timer should be engaged.

    Generating monotonically increasing time of day values in multiprocessors
    20.
    发明专利
    Generating monotonically increasing time of day values in multiprocessors 未知

    公开(公告)号：GB2502540A

    公开(公告)日：2013-12-04

    申请号：GB201209548

    申请日：2012-05-30

    Applicant: IBM

    Inventor： LEHNERT FRANK ,  JACOBI CHRISTIAN ,  GERWIG GUENTER ,  SHUM CHUNG-LUNG K ,  SLEGEL TIMOTHY J

    IPC: G06F1/14

    Abstract: Method for generating monotonically increasing time-OF-day (TOD) values in a multiprocessor system, comprising: receiving synchronization impulses 532; and refusing an execution of read instruction of a time-of-day value (STCK B) within processor 504 of the system if said execution is requested after a predefined time after a synchronization impulse, and if trigger signal 502a, indicative of new data received by a related memory 202 external to the processor, has been received after the predefined time. The predefined time is the smallest latency for data value transfer between processors. The memory is a shared cache. The synchronisation pulses are received from PLL 530. A time flag is set after the predetermined time is reached while a reject flag is set if time flag is set and the trigger signal is received. TOD execution is rejected if reject flag is set. Said flags are reset upon reception of synchronisation impulses.

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