公开(公告)号：JPH1039790A

公开(公告)日：1998-02-13

申请号：JP9898197

申请日：1997-04-16

Applicant: IBM

Inventor： ALT PAUL MATTHEW ,  CHALCO PEDRO A ,  FURMAN BRUCE KENNETH ,  HORTON RAYMOND ROBERT ,  NARAYAN CHANDRASEKHAR ,  OWENS BENAL LEE JR ,  WARREN KEVIN WILSON ,  WRIGHT STEVEN LORENZ

IPC: G02F1/1343 ,  G02F1/13 ,  G02F1/1362 ,  G06F11/20 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To make possible easily and inexpensively repairing an omission in a data line by selectively activating a selected non-committed data driver and providing a data signal on a conductive line. SOLUTION: In an array 32, the number of output lines of respective data drivers 36 are increased for adding an auxiliary driver to a glass panel 34. An electric connector used for connecting an LCD panel to a data source of a host computer, etc., requires a PROM chip selecting excess line only by a piece, and other PROM signals are multiplexed by existing lines. After reset, a controller 42 decides when the input data are lapped in a temporary memory from an address in a defective map for using on an auxiliary line 38. The data supplied to a display are corrected related to defective line information stored in the memory, and the selected non-committed data driver 36 is a ctivated selectively, and the data signal is provided on the conductive line.

公开(公告)号：JP2005175479A

公开(公告)日：2005-06-30

申请号：JP2004353505

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  CHIRAS STEFANIE R ,  COLBURN MATTHEW EARL ,  DALTON TIMOTHY JOSEPH ,  HEDRICK JEFFREY CURTIS ,  HUANG ELBERT EMIN ,  KUMAR KAUSHIK A ,  LANE MICHAEL WAYNE ,  MALONE KELLY ,  NARAYAN CHANDRASEKHAR ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  ROSENBERG ROBERT ,  TYBERG CHRISTY S ,  YU ROY RONGQING

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which reduces the dielectric constant between conductive lines by providing an air dielectric. SOLUTION: In a multilevel microelectronic integrated circuit, air comprises a permanent line level dielectric, and an ultra-low-k material constitutes a via level dielectric. In the IC structure, air is supplied to the line level after removal of a sacrificial material by clean thermal decomposition and auxiliary diffusion of byproducts through porosities. Optionally, air is also included within porosities in the via level dielectric. By incorporating air into the extension produced in the invention, intralevel and interlevel dielectric values are minimized. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过提供空气电介质来降低导线之间的介电常数的结构。 解决方案：在多电平微电子集成电路中，空气包括永久线路电平介质，超低k材料构成通孔级电介质。 在IC结构中，通过清洁的热分解和副产物通过孔隙的辅助扩散除去牺牲材料之后，空气被提供给线路层。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气并入本发明中生产的延伸中，使层内和层间介电值最小化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：JP2001057085A

公开(公告)日：2001-02-27

申请号：JP2000210249

申请日：2000-07-11

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL SUTORASUKA ,  NARAYAN CHANDRASEKHAR ,  WILLIAM TONTEI ,  CLAUDE BARTIN ,  NICK BANHIIRU

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a partially non-volatile dynamic random access memory(PNDRAM). SOLUTION: A partially non-volatile dynamic random access memory PNDRAM uses a DRAM array formed by plural single transistors 1T cells or two transistors 2T cells. The cell is electrically programmable as a non- volatile memory. Therefore, single chip design characteristic of both of a dynamic random access memory DRAM and an electrically programmable read only memory EPROM can be obtained. A DRAM and an EPROM integrated into a PNDRAM can be always and easily reconstituted during manufacturing or in a market. The PNDRAM has plural applications as a single chip such as a main memory related to ID, BIOS, or operating system information and the like.

公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JP2000243213A

公开(公告)日：2000-09-08

申请号：JP2000046289

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WEBER STEFAN J ,  IGGULDEN ROY ,  NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL CHRISTOPH ,  HOINKIS MARK ,  VAN DEN BERG ROBERT

IPC: H01H85/00 ,  H01H69/02 ,  H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a method for shrinking an area for a fuse to occupy on a semiconductor tip, and to adjust a fuse resistance relative to a fuse of a semiconductor device. SOLUTION: A fuse for a semiconductor is formed, so as to have a substrate 12 having a conductive passage disposed on its surface, a dielectric layer 14 disposed on the substrate, and a vertical fuse 110 vertically disposed on the surface. The vertical fuse penetrates through the dielectric layer 14 and is connected to the conductive passage. The vertical fuse also has a hole 108, a liner material is disposed on its vertical surface, and the fuse is cut off with fusing of the liner material along the vertical surface.

公开(公告)号：JP2004193614A

公开(公告)日：2004-07-08

申请号：JP2003409522

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL PATRICK ,  DENNARD ROBERT H ,  DIVAKARUNI RAMA ,  FURMAN BRUCE KENNETH ,  JAMMY RAJARAO ,  NARAYAN CHANDRASEKHAR ,  PURUSHOTHAMAN SAMPATH ,  SHEPARD JR JOSEPH F ,  TOPOL ANNA WANDA

IPC: H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

Abstract: PROBLEM TO BE SOLVED: To provide a structure for an integrated carrier equipped with high frequency and high speed passive components for computing. SOLUTION: A carrier 200 for a semiconductor component 102 is provided, which has passive components 3010 integrated in its substrate. The passive components 3010 include decoupling components, such as capacitors and resistors. A set of connections 210 is integrated in a close electrical proximity to the supported components. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000252364A

公开(公告)日：2000-09-14

申请号：JP2000047093

申请日：2000-02-24

Applicant: IBM ,  SIEMENS AG

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

公开(公告)号：JP2000091438A

公开(公告)日：2000-03-31

申请号：JP23860699

申请日：1999-08-25

Applicant: SIEMENS AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  EINSPRUCH FRED

IPC: H01L21/82 ,  G11C29/04 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/00 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To enable electrical fusion at the voltage of a specific value by connecting a fuse link at its one end with an individual connector terminal having a sectional region larger than its sectional region, and by connecting the fuse link at its other end with a common connector terminal having a sectional region which is larger than that of the sectional region of the individual connector terminal. SOLUTION: A semiconductor device 40 includes a board 41, on whose surface there is provided a redundant operating wiring, including many fuse-links 44 or a fuse bank used as a severe pitch array 42 for custom wirings. The fuse link 44 is connected at its one end with an individual connector terminal 43, having a sectional region about twice as large as its sectional region to be connected at its other end, with a common connector terminal 45 having a sectional region about twice as large as that of the individual connector terminal 43. As a result, heating caused by the maximized resistance difference between the fuse link 44 and the common connector terminal 45 is promoted to make possible electrical fusion at a voltage of about 10 V.

公开(公告)号：JPH11274158A

公开(公告)日：1999-10-08

申请号：JP4899

申请日：1999-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。