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公开(公告)号：DE3277156D1
公开(公告)日：1987-10-08
申请号：DE3277156
申请日：1982-05-24
Applicant: IBM
Inventor： REISMAN ARNOLD , BERKENBLIT MELVIN , MERZ CHARLES JOSEPH
IPC: H01L23/42 , H01L23/44 , H01L23/473
Abstract: A heat dissipating system for cooling circuit chips or modules is described. The system includes circuit chips (30) which are vertically mounted, an inert gas (40) at an elevated pressure being contained within an encased module (20) for providing an enhanced thermal coupling between the chips contained therein, and the walls (22, 26) of the encased module, whereby heat removal from the chips or modules is increased. This enhanced thermal coupling is combined with a reduction in the temperature of the wall (22) of the encased modules so as to reduce the thermal resistance between the surrounding gas and the chips or modules to be cooled, whereby heat removal from the circuit chips or modules is substantially increased. The gas is maintained at a pressure above 240 kPa (35 psi), preferably above 480 kPa (70 psi). Helium is a suitable thermally conducting inert gas.
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12.发明专利
公开(公告)号：DE3274301D1
公开(公告)日：1987-01-02
申请号：DE3274301
申请日：1982-05-24
Applicant: IBM
Inventor： ALTMAN CARL , BASSOUS ERNEST , OSBURN CARLTON M , PLESHKO PETER , REISMAN ARNOLD , SKOLNIK MARVIN B
Abstract: A mirror array light valve comprises a plurality of closely adjacent mirror elements (23) each supported by an individual one of a plurality of post members (19p) disposed in a regular array on a transparent substrate (10). The post members (19p) support the mirror elements (23) under corresponding corners thereof so that all the mirror elements are deflectable in the same direction thereby causing light reflected by the mirror elements to be directed to a single quadrant. The post members are preferably hollow straight- sided cylindrical silicon dioxide structures produced by a self-limiting etching process.
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13.发明专利
公开(公告)号：DE3067661D1
公开(公告)日：1984-06-07
申请号：DE3067661
申请日：1980-01-16
Applicant: IBM
Inventor： CROWDER BILLY , REISMAN ARNOLD
IPC: H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/331 , H01L21/336 , H01L23/29 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/43 , H01L29/49 , H01L29/73 , H01L21/283 , H01L29/54
Abstract: An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer integrated circuit devices. Such interconnecting members are useable to produce field effect transistor type devices.
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公开(公告)号：CA1161964A
公开(公告)日：1984-02-07
申请号：CA381224
申请日：1981-07-07
Applicant: IBM
Inventor： REISMAN ARNOLD , SILVESTRI VICTOR J , TANG DENNY D , WIEDMANN SIEGFRIED K , YU HWA N
IPC: H01L29/73 , H01L21/20 , H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8226 , H01L27/082 , H01L29/423 , H01L29/72 , H01L21/28
Abstract: ?79-055 QUASI-SYMMETRICAL BIPOLAR TRANSISTOR STRUCTURE A symmetrical vertical bipolar transistor circuit is provided wherein the top junction and the bottom junctions are self-aligned. Both the top and bottom junctions of the bipolar transistor have substantially equal areas, thereby eliminating parasitic diodes. A method for fabricating the symmetrical bipolar transistor is also described, which includes preferred steps for self-alignment and simultaneous deposition of single crystal and polycrystalline regions.
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公开(公告)号：CA1101765A
公开(公告)日：1981-05-26
申请号：CA305345
申请日：1978-06-13
Applicant: IBM
Inventor： BERKENBLIT MELVIN , CHAN SEE A , REISMAN ARNOLD , ZIRINSKY STANLEY
IPC: B05B1/00 , B41J2/135 , C04B41/53 , C04B41/91 , C23F1/00 , G01F1/42 , H01L21/308 , H03H7/06 , C09K13/04 , B01J17/00
Abstract: - PROCESS FOR ETCHING HOLES A method for etching at least one aperture having a defined crystallographic geometry in single crystals which includes masking the crystal to protect predetermined portions thereof from being etched, and then anisotropically etching with a mixture of sulfuric acid and phosphoric acid.
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Patent Agency Ranking
公开(公告)号：FR2395820A1
公开(公告)日：1979-01-26
申请号：FR7816947
申请日：1978-05-29
Applicant: IBM
Inventor： BERKENBLIT MELVIN , CHAN SEE ARK , REISMAN ARNOLD , ZIRINSKY STANLEY
IPC: B05B1/00 , B41J2/135 , C04B41/53 , C04B41/91 , C23F1/00 , G01F1/42 , H01L21/308 , H03H7/06 , B28D5/06 , B41J3/04
Abstract: A method for etching at least one aperture having a defined crystallographic geometry in single crystals which includes masking the crystal to protect predetermined portions thereof from being etched, and then anisotropically etching with a mixture of sulfuric acid and phosphoric acid.
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公开(公告)号：FR2317758A1
公开(公告)日：1977-02-04
申请号：FR7618339
申请日：1976-06-09
Applicant: IBM
Inventor： BERKENBLIT MELVIN , LUSSOW ROBERT O , PARK KYU C , REISMAN ARNOLD
Abstract: An in situ process is disclosed for fabricating gas discharge display panels in a sequential seal, bake-out and backfill mode of operation. The single thermal cycle process involves placing unassembled panel parts in a controlled gas ambient furnace system with required seal frame, evacuating said furnace and backfilling with an appropriate ambient atmosphere to an appropriate pressure while heating the furnace. During the heating, the furnace is repeatedly evacuated to moderate vacuum and refilled to some predetermined pressure. The furnace is heated to just above the glass transition temperature of the seal frame in this evacuate-refill mode, then held for some time to achieve outgassing of both panel parts and furnace chamber. Thereafter, the furnace chamber is refilled to one atmosphere and further heated to complete the sealing of the panel. The panel is then cooled to approximately 300 DEG C, still under one atmosphere, after which the evacuate-refill cycle is continuously repeated as the temperature is lowered down to the temperature of tip-off using the refill gas for the pressurization. The panel is refilled to an appropriate pressure at elevated temperature such that at room temperature the pressure is the desired pressure and the panel is tipped off. The process of successive evacuations and backfillings at the appropriate portions of the cycle are highly desirable for cleaning of the panel parts via contaminant dilution.
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公开(公告)号：DE2151073A1
公开(公告)日：1972-04-20
申请号：DE2151073
申请日：1971-10-13
Applicant: IBM
Inventor： BERKENBLIT MELVIN , REISMAN ARNOLD
Abstract: A polishing method for single crystal dielectrics such as sapphire and magnesium spinel is disclosed. A single crystal wafer of sapphire or magnesium spinel is immersed in a mixture of sulphuric and phosphoric acid in a range of mixtures of 9 parts sulphuric acid to 1 part phosphoric acid to 1 part sulphuric acid to 9 parts phosphoric acid by volume while the mixture is held at a temperature in the range of 200 DEG -325 DEG C. The rate of polishing as well as the quality of polishing of the wafers of sapphire or magnesium spinel is orientation sensitive and polishing is achieved for magnesium spinel having the orientations (100) and (110). Polishing is achieved for sapphire having the orientations (0001), (1123), (1100), (1124), (1120) and (0112). A wafer to be polished is suspended in the heated solution and may be rotated slowly. Nonpreferential material removal rates of fractions of a micron per minute are obtained. Crystals of both sapphire and spinel having the above-mentioned orientations may be polished in a preferred temperature range of 250 DEG -300 DEG C. The preferred polishing mixture for sapphire is 1 part sulphuric acid to 1 part phosphoric acid by volume at a temperature of 285 DEG C. For magnesium spinel, the preferred mixture is 3 parts sulphuric acid to 1 part phosphoric acid at a temperature of 250 DEG C. The polishing technique of the present invention provides planar, polished surfaces which are free of insoluble residues on the polished surface.
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