公开(公告)号：BR112022021777A2

公开(公告)日：2022-12-13

申请号：BR112022021777

申请日：2021-04-30

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: H01L29/78 ,  H01L21/336

Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

公开(公告)号：GB2606919A

公开(公告)日：2022-11-23

申请号：GB202209965

申请日：2020-12-14

Applicant: IBM

Inventor： TAKASHI ANDO ,  RUILONG XIE ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L45/00

Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes (110, 108) electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material (106) is disposed between the top and bottom electrodes (110, 108) of the RRAM structure. The resistive switching material (106) exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers (324) are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer (326) formed on an upper surface of the dielectric spacers (324) and covering at least a portion of sidewalls of the top electrode (110). The passivation layer (326) is self-aligned with the first metal connection line.

公开(公告)号：GB2604807A

公开(公告)日：2022-09-14

申请号：GB202207280

申请日：2020-10-23

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  MICHAEL RIZZOLO ,  RUILONG XIE

IPC: G11C11/16

Abstract: A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structure of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line (MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e. a MOL dielectric material).

公开(公告)号：GB2579487B

公开(公告)日：2021-12-15

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/768 ,  H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2595125A

公开(公告)日：2021-11-17

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET)architecture that includes a center fin region and one or more vertically stacked nanosheets.In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate.The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers.A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers.The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers.The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：GB2632937A

公开(公告)日：2025-02-26

申请号：GB202414140

申请日：2023-02-10

Applicant: IBM

Inventor： RUILONG XIE ,  NICOLAS JEAN LOUBET ,  JULIEN FROUGIER ,  DECHAO GUO

IPC: H10D88/00 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A semiconductor structure including a first stacked transistor structure including a top device stacked directly above a bottom device, and a second stacked transistor structure adjacent to the first stacked transistor, the second stacked transistor including a top device stacked directly above a bottom device, where the top device of the first stacked transistor structure and the top device of the second stacked transistor structure are made from different gate dielectric materials, and where the bottom device of the first stacked transistor structure and the bottom device of the second stacked transistor structure are made from different gate dielectric materials.

公开(公告)号：GB2627706B

公开(公告)日：2024-12-11

申请号：GB202408528

申请日：2022-11-28

Applicant: IBM

Inventor： CHEN ZHANG ,  RUILONG XIE ,  JUNLI WANG ,  DECHAO GUO

IPC: G06F15/16 ,  G11C11/412 ,  G11C11/417 ,  H10B10/00

Abstract: A compact SRAM design in a stacked architecture is provided. Notably, a 6-transistor SRAM bite cell including a bottom device level containing bottom field effect transistors and a top device level, stacked above the bottom device level, containing top field effect transistors of a different conductivity type than the bottom field effect transistors is provided.

公开(公告)号：IL297096A

公开(公告)日：2022-12-01

申请号：IL29709622

申请日：2022-10-06

Applicant: IBM ,  RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG SHENG KANG

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: B82Y10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：GB2600316A

公开(公告)日：2022-04-27

申请号：GB202200795

申请日：2020-06-15

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

IPC: H01L29/00 ,  H10B10/00

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

公开(公告)号：SG2013068614A

公开(公告)日：2014-09-26

申请号：SG2013068614

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC ,  IBM

Inventor： RUILONG XIE ,  CHANRO PARK ,  SHOM PONOTH

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.