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    11.
    发明专利
    未知

    公开(公告)号：DE69609283D1

    公开(公告)日：2000-08-17

    申请号：DE69609283

    申请日：1996-10-25

    Applicant: SIEMENS AG ,  IBM

    Inventor： PESCHKE MATTHIAS L ,  GAMBINO JEFFREY ,  RYAN JAMES GARDNER ,  STENGL REINHARD JOHANNES

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/60

    Abstract: A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole. The remaining portion of the insulating layer which extends between the contact hole and the first conductor level is then etched to extend the contact hole to the first conductor level. The spacer substantially prevents the erosion of the pair of spaced apart segments during the etching of the remaining portion of the insulating layer. The contact hole is then filled with a conductive material to form the self-aligned borderless contact. The borderless contact formed by the present method is electrically isolated from the pair of spaced apart conducting segments of the patterned conductor level by the dielectric insulating layer.

    14.
    发明专利
    未知

    公开(公告)号：DE69534699D1

    公开(公告)日：2006-01-26

    申请号：DE69534699

    申请日：1995-09-22

    Applicant: IBM

    Inventor： DOBUZINSKY DAVID MARK ,  MATSUDA TETSUO ,  VAN NGUYEN SON ,  RYAN JAMES GARDNER

    IPC: C23C16/30 ,  C23C16/40 ,  C23C16/505 ,  H01L21/31 ,  H01L21/316

    Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element. In particular, comparison between traces of undoped oxide and fluorosilicate glass clearly shows that the former has a greater SIOH concentration which is a manufacturing yield detractor.

    15.
    发明专利
    未知

    公开(公告)号：DE69217702T2

    公开(公告)日：1997-10-23

    申请号：DE69217702

    申请日：1992-04-16

    Applicant: SIEMENS AG ,  IBM

    Inventor： RYAN JAMES GARDNER ,  STRIPPE DAVID CRAIG ,  VOLLMER BERND MICHAEL

    IPC: H01L21/285 ,  C23C14/04 ,  H01J37/32 ,  H01J37/34 ,  H01L21/768 ,  H05K3/40

    Abstract: A sputtering deposition wherein high aspect ratio apertures are coated with conductive films exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator is used having an aspect ratio that approximates the aspect ratio of the apertures. The resulting film thickness at the bottom of the aperture is at least 2X what can be achieved using conventional sputtering methods. The amount of material deposited at the bottom of the apertures can be further enhanced by elevating the temperature of the substrate (e.g. 450 C) during the deposition process.

    17.
    发明专利
    未知

    公开(公告)号：DE3482679D1

    公开(公告)日：1990-08-16

    申请号：DE3482679

    申请日：1984-08-23

    Applicant: IBM

    Inventor： ISHAQ MOUSA HANNA ,  ROBERTS STANLEY ,  RYAN JAMES GARDNER

    IPC: H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/60

    Abstract: @ A method for diffusing a conductivity determining impurity in a semiconductor substrate (10) and making electrical contact thereto by depositing a layer (18) of a rare earth boride material over a predetermined surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the boride material to diffuse into the adjoining portion of the substrate (20, 22) to modify its conductive characteristics. At the same time a good electrical ohmic contact is established between the boride material and the adjoining substrate portion while the boride material retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.

    18.
    发明专利
    未知

    公开(公告)号：DE69415476T2

    公开(公告)日：1999-07-15

    申请号：DE69415476

    申请日：1994-10-06

    Applicant: IBM

    Inventor： GEISS PETER JOHN ,  LICATA THOMAS JOHN ,  HO HERBERT LEI ,  RYAN JAMES GARDNER

    IPC: H01L21/28 ,  C30B1/00 ,  H01L21/223 ,  H01L21/225 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  C30B29/10 ,  C30B1/02

    Abstract: A process for forming an epitaxial cobalt silicide (CoSi2) film in a semiconductor device, comprises: (a) forming on the Si substrate (10) a layer of refractory metal (12) comprising W, Cr, Mo or mixts. or silicides thereof; (b) forming a Co layer (14); and (c) annealing the Co layer at a temp. high enough to form epitaxial CosI2 film (16) overlying the substrate. A process for forming epitaxial CoSi2 by forming a W layer, followed by a Co layer, on a Si substrate, followed by annealing at 550[deg]C. for a time long enough to form epitaxial CoSi2.

    19.
    发明专利
    未知

    公开(公告)号：DE69415476D1

    公开(公告)日：1999-02-04

    申请号：DE69415476

    申请日：1994-10-06

    Applicant: IBM

    Inventor： GEISS PETER JOHN ,  LICATA THOMAS JOHN ,  HO HERBERT LEI ,  RYAN JAMES GARDNER

    IPC: H01L21/28 ,  C30B1/00 ,  H01L21/223 ,  H01L21/225 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  C30B29/10 ,  C30B1/02

    Abstract: A process for forming an epitaxial cobalt silicide (CoSi2) film in a semiconductor device, comprises: (a) forming on the Si substrate (10) a layer of refractory metal (12) comprising W, Cr, Mo or mixts. or silicides thereof; (b) forming a Co layer (14); and (c) annealing the Co layer at a temp. high enough to form epitaxial CosI2 film (16) overlying the substrate. A process for forming epitaxial CoSi2 by forming a W layer, followed by a Co layer, on a Si substrate, followed by annealing at 550[deg]C. for a time long enough to form epitaxial CoSi2.

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