公开(公告)号：JPS57107070A

公开(公告)日：1982-07-03

申请号：JP14408181

申请日：1981-09-14

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

公开(公告)号：JPH07201979A

公开(公告)日：1995-08-04

申请号：JP30050794

申请日：1994-12-05

Applicant: IBM

Inventor： KIYARORU GARI ,  RUISU RUU-CHIEN SUU ,  SEIKI OGURA ,  JIYOSEFU FURANSHISU SHIEPAADO

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08

Abstract: PURPOSE: To provide a shallow groove separation structure formed by a process having the reduced number of processing processes and heat balance. CONSTITUTION: A groove is packed with the liquid accumulation of an insulating semiconductor oxide, the heat treatment of the accumulated oxide is operated, and a thermal oxide layer 30 of high quality is formed on a boundary face between the accumulated oxide film and a substrate 12. This process applies a separation structure for reducing stresses and charge leakages. When a grinding stop layer 14 is provided on a semiconductor material main body, this structure can be easily made flat. The void of the accumulated oxide and a contaminant can be almost removed by self-aligned accumulation on the groove within the capacity of an opening on resist used for forming the groove.

公开(公告)号：JPH07169775A

公开(公告)日：1995-07-04

申请号：JP18564294

申请日：1994-08-08

Applicant: IBM

Inventor： SHIYAA AAKUBAA ,  PATORISHIA RABERII KUROOSEN ,  SEIKI OGURA ,  NIIIBO ROBEDO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PURPOSE: To provide a bipolar transistor in which a structure with a base contact point extending-layer which extends to one side of an emitter and a subcollector extending-layer extending to the other side is provided, and no collector reacting through contact point is contained, enabling manufacturing with high integration density using a polysilicon emitter. CONSTITUTION: A subcollector layer 26 formed on an epitaxial layer 34, a collector layer 12 in contact with a subcollector layer 28, a base layer 14 on the collector layer 12 and a polysilicon emitter layer 16 on the base layer are contained. A base contact point extension layer 22 is provided, while being brought into contact with the base layer 14, and a top surface 62 thereof is put in a position lower than the lower surface of the emitter layer 16, so that the breakdown voltage of an emitter base is raised. A subcollector extension layer 30 in contact with the subcollector layer 26 is provided on the side opposite to the base contact point extension layer 22. Sidewall insulating-layers 18 and 20 are formed on a sidewall of an emitter, and mutually connected conductors 24 and 29 of a base and a collector are separated from the emitter.

公开(公告)号：JPH05251385A

公开(公告)日：1993-09-28

申请号：JP33132892

申请日：1992-12-11

Applicant: IBM

Inventor： POORU SEKUUON KIMU ,  SEIKI OGURA

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/90

Abstract: PURPOSE: To provide a method for mutual connection between the local parts of adjacent devices on a semiconductor substrate by changing an insulating layer to a conductive layer. CONSTITUTION: An electrically insulating etch stop layer 26 is stuck to the surface of a semiconductor substrate including a device contact aperture. A conductive layer is stuck to the surface of the etch stop layer 26. A local mutual connection pattern is formed on the conductive layer by using the patterning (30, 30") of the resist and a subtractive etching to be stopped at the layer 26. The conductive pattern and its lower side insulating material 26 interact with each other by heat activation and a single conductive layer (32, 32") is formed.

公开(公告)号：JPH04118966A

公开(公告)日：1992-04-20

申请号：JP25545990

申请日：1990-09-27

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To manufacture a high-speed dynamic RAM using optical lithography by forming an N -type region by performing ion implantation of an N -type impurity before the ion implantation process of an N -impurity. CONSTITUTION: An insulator region 11 that extending toward the upper part of the surface of a body and is arranged with a gap is provided at the single- crystal silicon body. A polysilicon gate electrode 13 having basically a vertical surface is formed between adjacent insulator regions. An N -type impurity is subjected to ion implantation, and an N -type impurity region is formed between the vertical surface of the gate electrode and the insulator region. After that, by forming an insulator layer 16 at the top of the horizontal surface of the single-crystal silicon body, a nearly vertical surface is formed adjacently on a nearly horizontal surface. After that, finally insulator layer 16 formed is subjected to reaction ion etching, all of insulator layer 16 that is arranged nearly horizontally are eliminated, an insulator region with a narrow dimension being adjacent to a nearly vertical surface or a side wall spacer 20 is left, and an N -type impurity located at a lower side is protected from the later ion implantation of an N -type impurity.

公开(公告)号：JPH02268016A

公开(公告)日：1990-11-01

申请号：JP5288890

申请日：1990-03-06

Applicant: IBM

Inventor： JIERAARU BUDON ,  PIEERU MORIE ,  SEIKI OGURA ,  DOMINIIKU OME ,  PASUKARU TANOFU ,  FURANKU WARAARU

IPC: H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

Abstract: PURPOSE: To quicken the operating speed and to reduce current consumption by providing a voltage converter circuit between NPN and PNP output transistors(TRs), selecting a DC voltage shift to be a shift to warrant both a minimum crossover current and a minimum delay and setting the shift point to be an operating point. CONSTITUTION: Two output bipolar TRs, an upper NPNT 1 and a lower PNPT 2 are connected by a common coupling node N and a 1st power supply voltage VH and a 2nd power supply voltage GND are given to both ends of the TRs T1, T2. The output node N is connected to a terminal 15, at which an output signal VOUT is available and a voltage conversion circuit SA1 is placed between a base and a node of each TR. Then the base node is driven by a logic signal IN 1 fed from a preceding drive circuit and the complementary emitter follower driver is operated at a conduction limit independently of a threshold level of the TRs.

公开(公告)号：JPH08340095A

公开(公告)日：1996-12-24

申请号：JP13220196

申请日：1996-05-27

Applicant: IBM

Inventor： SEIKI OGURA ,  NIBO ROBEDO ,  ROBAATO SHII UON

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a process for manufacturing a high-density memory array. SOLUTION: N-type impurities are implanted in a P-type substrate, and continuous diffused rails 24, which have a substantially flat outline, are formed. A bit line, which corresponds to each rail 24, is specified by the rail 24. Source and drain regions of each adjacent memory array cell pair, which is related with each bit line, are specified by each rail. In one mode, a plurality of polysilicon layers are used for forming control gates, a floating gate 18, sources and drains. The polysilicon layers are self-aligned with each other, so as to substantially reduce an overlapping of the polysilicon layers for minimizing the parasitic capacitance of a memory array. Domino and and skippy domino mechanisms are used for programming a memory array cell and for reading out the programming. A comparatively low programming voltage is used for the programming, and the programming is realized by a channel hot electron tunneling phenomenon.

公开(公告)号：JPH08115988A

公开(公告)日：1996-05-07

申请号：JP25618895

申请日：1995-10-03

Applicant: IBM

Inventor： JIYOISU ERIZABESU AKOOSERA ,  KIYARORU GARI ,  RUISU RUU CHIEN SUU ,  SEIKI OGURA ,  NIBUO ROBUEDOO ,  JIYOSEFU FURANSHISU SHIEPAADO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve packaging density, performance, and manufacturing yield in an electrically erasable EEPROM by confining a floating gate structure between separation structures that are covered with a thin nitride layer. SOLUTION: A floating gate 24 is entrapped by making flat up to the surface of nitride layer by the self-limiting chemical/mechanical polishing process. Then, the connection of a gate oxide 25 and a control electrode 26 is formed on a nearly flat surface. Since a halsh topography on a surface where the connection is formed can be avoided, a low-resistance connection including a metallic connection can be formed appropriately, thus reducing the transistor of a memory cell.

公开(公告)号：JPH07254653A

公开(公告)日：1995-10-03

申请号：JP11110493

申请日：1993-04-14

Applicant: IBM

Inventor： TAKI NASERU BUCHI ,  RUISU RUUCHIEN SHIYU ,  MAAKU EDOUIN JIYOSUTO ,  SEIKI OGURA ,  RONARUDO NOOMAN SHIYURUTSU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786

Abstract: PURPOSE: To form a thin silicon region for a CMOS and a thick silicon region for a bipolar region into an epitaxial device layer. CONSTITUTION: A set of oxide islands 20 is formed onto a first wafer. An epitaxial layer 30 is grown from a bipolar silicon region, and the oxide islands 20 are coated. The process is used as a step, when the bottom section of a bipolar region is formed. The first wafer is inverted, and an oxide is coupled with a second wafer 60 by the new grown epitaxial layer 30 in the lower sections of the oxide islands 20. Consequently, a new top face is formed in a high-quality epitaxial layer. Excess silicon is removed from the new top face, the top face is polished by using a nitride polishing stop layer until thickness on the oxide islands 20 reaches 1000 (Å), and the thick epitaxial silicon layer of 1 (μm) is left in the bipolar region, while the epitaxial silicon layer of thickness 1000 (Å) is left in a CMOS region.

公开(公告)号：JPH0661493A

公开(公告)日：1994-03-04

申请号：JP13053693

申请日：1993-06-01

Applicant: IBM

Inventor： CHIYANNMIN SHII ,  RUISU ERUUSHII SHIYUU ,  SEIKI OGURA

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE: To provide a field-effect transistor(FET) having a vertical gate and a very thin channel sandwiched between a source layer and a drain layer. CONSTITUTION: An FET is formed on a silicon-on-insulator(SOI) substrate having an Si layer 12 acting as a first layer, e.g. source layer. A very thin channel 22 (e.g. of 0.1 μm) is formed by a low temp. epitaxial(LTE) process. A chemical vapor deposition polysilicon layer 28 forms a top layer (e.g. drain layer). An opening is etched through the three layers down to an insulation substrate and the opening wall is oxidized to form a gate oxide layer 33. Polysilicon fills the openings and is deposited to form a vertical gate 34.